[all-commits] [llvm/llvm-project] 79d0de: [CodeGen][NewPM] Port `machine-loops` to new pass ...

[paperchalice via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79d0de2ac37b6b7d66720611935d1dd7fc4fbd43
      https://github.com/llvm/llvm-project/commit/79d0de2ac37b6b7d66720611935d1dd7fc4fbd43
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2024-07-09 (Tue, 09 Jul 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineLoopInfo.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    M llvm/lib/CodeGen/BranchFolding.cpp
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
    M llvm/lib/CodeGen/MIRSampleProfile.cpp
    M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
    M llvm/lib/CodeGen/MachineBlockPlacement.cpp
    M llvm/lib/CodeGen/MachineCombiner.cpp
    M llvm/lib/CodeGen/MachineLICM.cpp
    M llvm/lib/CodeGen/MachineLoopInfo.cpp
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/CodeGen/MachineTraceMetrics.cpp
    M llvm/lib/CodeGen/ModuloSchedule.cpp
    M llvm/lib/CodeGen/PHIElimination.cpp
    M llvm/lib/CodeGen/PeepholeOptimizer.cpp
    M llvm/lib/CodeGen/PostRASchedulerList.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/RegAllocPBQP.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/ShrinkWrap.cpp
    M llvm/lib/CodeGen/StackSlotColoring.cpp
    M llvm/lib/CodeGen/UnreachableBlockElim.cpp
    M llvm/lib/CodeGen/XRayInstrumentation.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
    M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
    M llvm/lib/Target/AMDGPU/R600Packetizer.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
    M llvm/lib/Target/ARM/ARMBlockPlacement.cpp
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
    M llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
    M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    M llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
    M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
    M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
    M llvm/lib/Target/X86/X86CmovConversion.cpp
    M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
    M llvm/lib/Target/X86/X86PreTileConfig.cpp
    A llvm/test/CodeGen/X86/machine-loops.ll

  Log Message:
  -----------
  [CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)

- Add `MachineLoopAnalysis`.
- Add `MachineLoopPrinterPass`.
- Convert to `MachineLoopInfoWrapperPass` in legacy pass manager.



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