[all-commits] [llvm/llvm-project] eb76bc: [RISCV] Relax RISCVInsertVSETVLI output VL peeking...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eb76bc38ffc286e62fdb8f8d897b5de04b2575be
      https://github.com/llvm/llvm-project/commit/eb76bc38ffc286e62fdb8f8d897b5de04b2575be
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-06-23 (Sun, 23 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
    M llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll

  Log Message:
  -----------
  [RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (#96200)

If the AVL in a VSETVLIInfo is the output VL of a vsetvli with the same
VLMAX, we treat it as the AVL of said vsetvli.

This allows us to remove a true dependency as well as treating
VSETVLIInfos as equal in more places and avoid toggles.

We do this in two places, needVSETVLI and computeInfoForInstr. However
we don't do this in computeInfoForInstr's vsetvli equivalent,
getInfoForVSETVLI.

We also have a restriction only in computeInfoForInstr that the AVL
can't be a register as we want to avoid extending live ranges.

This patch does two interlinked things:

1) It adds this AVL "peeking" to getInfoForVSETVLI

2) It relaxes the constraint that the AVL can't be a register in
computeInfoForInstr, since it removes a use of the output VL which can
actually reduce register pressure. E.g. see the diff in
@vector_init_vsetvli_N and @test6

Now that getInfoForVSETVLI and computeInfoForInstr are consistent, we
can remove the check in needVSETVLI.

We also need to update how we update LiveIntervals in insertVSETVLI, as
we can now end up needing to extend the LiveRange of the AVL across
blocks.



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