[all-commits] [llvm/llvm-project] 556610: AMDGPU: Materialize bitwise not of inline immediates

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu-shrink-instruction-bitwise-not-inline-immediate
  Home:   https://github.com/llvm/llvm-project
  Commit: 5566107f187d1e4151a01cfe7093aec509bc5850
      https://github.com/llvm/llvm-project/commit/5566107f187d1e4151a01cfe7093aec509bc5850
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-06-21 (Fri, 21 Jun 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
    M llvm/test/CodeGen/AMDGPU/permute_i8.ll
    M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
    M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll

  Log Message:
  -----------
  AMDGPU: Materialize bitwise not of inline immediates

If we have a bitwise negated inline immediate, we can materialize
it with s_not_b32/v_not_b32. This mirrors the current bitreverse
handling.

As a side effect, we also now handle the bitreversed FP immediate
case.

One test shows some VOPD regressions on gfx11 which should
probably be fixed. Previously the 2 v_mov_b32 could be packed,
but now the mismatched opcode + mov can't. This problem already
already existed for the bfrev case, it just happens more often now.



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