[all-commits] [llvm/llvm-project] 214e6b: [SPIR-V] Inline assembly support (#93164)

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 214e6b40f8487cec03ab5d211369d8836de0ef68
      https://github.com/llvm/llvm-project/commit/214e6b40f8487cec03ab5d211369d8836de0ef68
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-05-24 (Fri, 24 May 2024)

  Changed paths:
    M llvm/docs/SPIRVUsage.rst
    M llvm/include/llvm/IR/IntrinsicsSPIRV.td
    M llvm/lib/Target/SPIRV/CMakeLists.txt
    M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
    M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
    M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
    A llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.cpp
    A llvm/lib/Target/SPIRV/SPIRVInlineAsmLowering.h
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
    M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
    M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
    M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
    M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
    M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
    M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
    A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll

  Log Message:
  -----------
  [SPIR-V] Inline assembly support (#93164)

This PR introduces support for inline assembly calls for SPIR-V Backend
in general, and support for SPV_INTEL_inline_assembly [1] extension in
particular. The former part of the PR is agnostic towards
vendor-specific requirements and resolves the task of supporting
successful transformation of inline assembly as long as it's possible
without specific SPIR-V instruction codes.

As a part of the PR there appears an opportunity to bring coherent
inline assembly information up to latest passes of the transformation
process (emitting final SPIR-V instructions), so that PR makes it easy
to add any another required flavor of inline assembly, other then
supported by the vendor specific SPV_INTEL_inline_assembly extension,
if/when needed.

At the moment, however, SPV_INTEL_inline_assembly is the only
implemented way to bring LLVM IR inline assembly calls up to valid
SPIR-V instructions and also the default one. This means that inline
assembly calls will generate an error message of such extension is not
used to prevent LLVM-generated error messages at the final stages of
translation. When the SPV_INTEL_inline_assembly extension is mentioned
among supported, translation of inline assembly is intercepted by this
extension implementation on a pre-legalizer step, and this is a place
where support for a new inline assembly extension may be added if
needed.

This PR also extends support for register classes, improves type
inference during pre-legalizer pass, and fixes a minor bug with
asm-printing of string literals.

[1]
https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc



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