[all-commits] [llvm/llvm-project] 097e96: [LegalizeTypes] Use VP_AND for zext_inreg in Promo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 097e96d0d1ad9cceb461bb3487af0a2ec42176e4
      https://github.com/llvm/llvm-project/commit/097e96d0d1ad9cceb461bb3487af0a2ec42176e4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-20 (Mon, 20 May 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

  Log Message:
  -----------
  [LegalizeTypes] Use VP_AND for zext_inreg in PromoteIntRes_VPFunnelShift.

I may eventually add getVPZeroExtendInReg to SelectionDAG if there are
other cases, but for now just hardcode it.



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