[all-commits] [llvm/llvm-project] de14b7: [RISCV][test] Precommit tests for byte store of -1

Tue May 14 11:55:25 PDT 2024

  Branch: refs/heads/users/nuriamari/fix-lto-ObjC
  Home:   https://github.com/llvm/llvm-project
  Commit: de14b749fee41d4ded711e771e43043ae3100cb3
      https://github.com/llvm/llvm-project/commit/de14b749fee41d4ded711e771e43043ae3100cb3
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  -----------
  [RISCV][test] Precommit tests for byte store of -1

Although we can't reduce the number of instructions, if we selected `li
rd, -1` instead then this could be encoded in a 16-bit instruction.

  Commit: 90109d444839683b09f0aafdc50b749cb4b3203b
      https://github.com/llvm/llvm-project/commit/90109d444839683b09f0aafdc50b749cb4b3203b
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll

  Log Message:
  -----------
  [RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)

This follows the same pattern as 20e62658735a1b03ecadc. Although we
can't reduce the number of instructions used, if we are able to use a
sign-extended 6-bit immediate then the 16-bit c.li instruction can be
selected (thus saving code size). Although this _could_ be gated so it
only happens if C is enabled, I've opted not to because at worst it's
neutral and it doesn't seem helpful to add unnecessary divergence
between the RVC and non-RVC paths.

  Commit: 67d840b60fbd75ca1b52d77bd3353771ec853735
      https://github.com/llvm/llvm-project/commit/67d840b60fbd75ca1b52d77bd3353771ec853735
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    A llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll

  Log Message:
  -----------
  [VPlan] Relax over-aggressive assertion in VPTransformState::get().

There are cases where a vector value has some users that demand the
the single scalar value only (NeedsScalar), while other users demand the
vector value (see attached test cases). In those cases, the NeedsScalar
users should only demand the first lane.

Fixes https://github.com/llvm/llvm-project/issues/91883.

  Commit: f89b1b8a68065c4b880417abb0563bce21399b52
      https://github.com/llvm/llvm-project/commit/f89b1b8a68065c4b880417abb0563bce21399b52
  Author: Oleg Shyshkov <shyshkov at google.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [mlir][bazel] Fix bazel build.

  Commit: 19008d32182ebbe421aaa222ee8af5c3e134e550
      https://github.com/llvm/llvm-project/commit/19008d32182ebbe421aaa222ee8af5c3e134e550
  Author: PiJoules <6019989+PiJoules at users.noreply.github.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    A llvm/test/CodeGen/AArch64/smul_fix.ll
    A llvm/test/CodeGen/AArch64/smul_fix_sat.ll
    A llvm/test/CodeGen/AArch64/umul_fix.ll
    A llvm/test/CodeGen/AArch64/umul_fix_sat.ll

  Log Message:
  -----------
  [llvm] Support fixed point multiplication on AArch64 (#84237)

Prior to this, fixed point multiplication would lead to this assertion
error on AArhc64, armv8, and armv7.

```
 _Accum f(_Accum x, _Accum y) { return x * y; }

// ./bin/clang++ -ffixed-point /tmp/test2.cc -c -S -o - -target aarch64 -O3
clang++: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:10245: void llvm::TargetLowering::forceExpandWideMUL(SelectionDAG &, const SDLoc &, bool, EVT, const SDValue, const SDValue, const SDValue, const SDValue, SDValue &, SDValue &) const: Assertion `Ret.getOpcode() == ISD::MERGE_VALUES && "Ret value is a collection of constituent nodes holding result."' failed.
```

This path into forceExpandWideMUL should only be taken if we don't
support [US]MUL_LOHI or MULH[US] for the operand size (32 in this case).
But we should also check if we can just leverage regular wide
multiplication. That is, extend the operands from 32 to 64, do a regular
64-bit mul, then trunc and shift. These ops are certainly available on
aarch64 but for wider types.

  Commit: acd100747fff85e7cfb67caa6c0f1053e820c1ac
      https://github.com/llvm/llvm-project/commit/acd100747fff85e7cfb67caa6c0f1053e820c1ac
  Author: Felix Schneider <fx.schn at gmail.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M mlir/test/Dialect/Arith/int-range-interface.mlir
    M mlir/test/Dialect/Arith/int-range-opts.mlir
    M mlir/test/Dialect/GPU/int-range-interface.mlir
    M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
    M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
    M mlir/test/lib/Dialect/Test/TestOps.td

  Log Message:
  -----------
  [mlir][test] Extend `InferIntRangeInterface` test Ops to arbitrary ints (#91850)

This PR is in preparation to some extensions to the
`InferIntRangeInterface` around the `nsw` and `nuw` flags supported in
the `arith` dialect and LLVM.

We provide some common inference logic for `index` and `arith` in
`InferIntRangeCommon.h` but our Test Ops are currently fixed to `Index`
Types. As we test the range inference for arith Ops, especially around
the overflow behaviour, it's handy to have native support for the
typical integer types in the test Ops.

This patch
1. Changes the Attributes of `test.with_bounds` ops from `Index` to
`APInt` which matches the internal representation in
`ConstantIntRanges`.
2. Allows the use of `AnyInteger` in addition to `Index` for the
operands and results of the test Ops. This now requires explicit
specification of the type in the IR, where before `Index` was implicit.
3. Requires bounds Attrs to be specified in the precision of the SSA
value, eliminating any implicit truncation or extension. (*Could this
lead to problems?*)

  Commit: 80f8ae3f8485b62529c32683ca48822d700c7716
      https://github.com/llvm/llvm-project/commit/80f8ae3f8485b62529c32683ca48822d700c7716
  Author: Florian Mayer <fmayer at google.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/docs/MIRLangRef.rst

  Log Message:
  -----------
  [NFC] add explanation to register flags doc (#91803)

  Commit: 5adfcb07501f1d128e6517e60d30f2e3a0dc8eaa
      https://github.com/llvm/llvm-project/commit/5adfcb07501f1d128e6517e60d30f2e3a0dc8eaa
  Author: Zequan Wu <zequanwu at google.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M clang/utils/creduce-clang-crash.py

  Log Message:
  -----------
  Allow passing creduce options through creduce-clang-crash.py (#92141)

This change allows us to pass creduce options to creduce-clang-crash.py
script. With this, `--n` is no longer needed to specify the number of
cores, so removed the flag.

The motivation is
https://github.com/llvm/llvm-project/pull/87933#issuecomment-2109463497
suggests that disabling creduce renaming passes helps people to further
reduce crash manually.

  Commit: 179efe5abc745b5646efeb33fef86c55aa4fd7dc
      https://github.com/llvm/llvm-project/commit/179efe5abc745b5646efeb33fef86c55aa4fd7dc
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/lib/Analysis/LoopAccessAnalysis.cpp
    M llvm/test/Analysis/LoopAccessAnalysis/is-safe-dep-distance-with-loop-guards.ll

  Log Message:
  -----------
  [LAA] Delay applying loop guards until after isSafeDependenceDistance.

Applying the loop guards to the distance may prevent
isSafeDependenceDistance from determining NoDep, unless loop guards are
also applied to the backedge-taken-count.

Instead of applying the guards to both Dist and the
backedge-taken-count, just apply them after handling
isSafeDependenceDistance and constant distances; there is no benefit to
applying the guards before then.

This fixes a regression flagged by @bjope due to
ecae3ed958481cba7d60868cf3504292f7f4fdf5.

  Commit: d90efc5d45199e4471271cc30e4c1ee7797b0523
      https://github.com/llvm/llvm-project/commit/d90efc5d45199e4471271cc30e4c1ee7797b0523
  Author: Nuri Amari <nuriamari at meta.com>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M clang/utils/creduce-clang-crash.py
    M llvm/docs/MIRLangRef.rst
    M llvm/lib/Analysis/LoopAccessAnalysis.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/test/Analysis/LoopAccessAnalysis/is-safe-dep-distance-with-loop-guards.ll
    A llvm/test/CodeGen/AArch64/smul_fix.ll
    A llvm/test/CodeGen/AArch64/smul_fix_sat.ll
    A llvm/test/CodeGen/AArch64/umul_fix.ll
    A llvm/test/CodeGen/AArch64/umul_fix_sat.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    A llvm/test/Transforms/LoopVectorize/X86/widened-value-used-as-scalar-and-first-lane.ll
    M mlir/test/Dialect/Arith/int-range-interface.mlir
    M mlir/test/Dialect/Arith/int-range-opts.mlir
    M mlir/test/Dialect/GPU/int-range-interface.mlir
    M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
    M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
    M mlir/test/lib/Dialect/Test/TestOps.td
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  Merge branch 'main' into users/nuriamari/fix-lto-ObjC

Compare: https://github.com/llvm/llvm-project/compare/fa4ea0752998...d90efc5d4519

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