[all-commits] [llvm/llvm-project] ed16e7: [RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in g...

[Shih-Po Hung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ed16e7aac44f2024b45d8c6c9dc2817d77d0ea97
      https://github.com/llvm/llvm-project/commit/ed16e7aac44f2024b45d8c6c9dc2817d77d0ea97
  Author: Shih-Po Hung <shihpo.hung at sifive.com>
  Date:   2024-05-13 (Mon, 13 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
    M llvm/test/Analysis/CostModel/RISCV/arith-int.ll

  Log Message:
  -----------
  [RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost (#89170)

This patch made following changes:
1. Support ISD FDIV/UDIV/SDIV/UREM/SREM
2. Classify instructions which cost the same



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