[all-commits] [llvm/llvm-project] bbd6a2: [RISCV] Convert implicit_def tuples to noreg in po...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbd6a2d85c44d99e66b471d251a742f7551a0c61
      https://github.com/llvm/llvm-project/commit/bbd6a2d85c44d99e66b471d251a742f7551a0c61
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-05-08 (Wed, 08 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll

  Log Message:
  -----------
  [RISCV] Convert implicit_def tuples to noreg in post-isel peephole (#91173)

If a segmented load has an undefined passthru then it will be selected
as a reg_sequence with implicit_def operands, which currently slips
through the implicit_def -> noreg peephole.

This patch fixes this so we're able to infer if the passthru is
undefined without the need for looking through vreg definitions with
MachineRegisterInfo, which will help with moving RISCVInsertVSETVLI to
LiveIntervals in #70549



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