[all-commits] [llvm/llvm-project] 52187b: [RISCV] Move RISCVDeadRegisterDefinitions to post ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 52187b9f2e7ef0997269bcf64b3d2512a52467ed
      https://github.com/llvm/llvm-project/commit/52187b9f2e7ef0997269bcf64b3d2512a52467ed
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-05-07 (Tue, 07 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [RISCV] Move RISCVDeadRegisterDefinitions to post vector regalloc (#90636)

Currently RISCVDeadRegisterDefinitions runs after vsetvli insertion, but
in #70549 vsetvli insertion runs after vector regalloc and as a result
we no longer convert some vsetvli a0, a0s to vsetvli x0, a0. This patch
moves it to after vector regalloc, but before scalar regalloc so we
still get the benefits of reducing register pressure.



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