[all-commits] [llvm/llvm-project] bfc031: Move several vector intrinsics out of experimental...

[Maciej Gabka via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bfc0317153dca75137fba00b5c28758d6f720963
      https://github.com/llvm/llvm-project/commit/bfc0317153dca75137fba00b5c28758d6f720963
  Author: Maciej Gabka <maciej.gabka at arm.com>
  Date:   2024-04-29 (Mon, 29 Apr 2024)

  Changed paths:
    M clang/lib/CodeGen/CGExprScalar.cpp
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/IR/PatternMatch.h
    M llvm/lib/Analysis/InstructionSimplify.cpp
    M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/IR/IRBuilder.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
    M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll
    M llvm/test/Analysis/CostModel/AArch64/splice.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
    M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
    M llvm/test/Analysis/CostModel/RISCV/splice.ll
    A llvm/test/Bitcode/upgrade-vector-interleave2-deinterleave2-intrinsics.ll
    A llvm/test/Bitcode/upgrade-vector-reverse-intrinsic.ll
    A llvm/test/Bitcode/upgrade-vector-splice-intrinsic.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
    M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
    M llvm/test/Transforms/InstCombine/vector-reverse.ll
    M llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll
    M llvm/test/Transforms/InstSimplify/select.ll
    M llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll
    M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
    M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
    M llvm/test/Verifier/invalid-splice.ll
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
    M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
    M mlir/test/Dialect/LLVMIR/invalid.mlir
    M mlir/test/Dialect/LLVMIR/roundtrip.mlir

  Log Message:
  -----------
  Move several vector intrinsics out of experimental namespace (#88748)

This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.



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