[all-commits] [llvm/llvm-project] 16bd10: Revert "[SelectionDAG] Handle more opcodes in canC...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 16bd10a38730fed27a3bf111076b8ef7a7e7b3ee
      https://github.com/llvm/llvm-project/commit/16bd10a38730fed27a3bf111076b8ef7a7e7b3ee
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2024-04-29 (Mon, 29 Apr 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/combine-mul.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/abdu-vector-128.ll
    M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
    M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
    M llvm/test/CodeGen/X86/combine-mul.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/fold-masked-merge.ll
    M llvm/test/CodeGen/X86/freeze-binary.ll
    M llvm/test/CodeGen/X86/freeze-combine.ll
    M llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
    M llvm/test/CodeGen/X86/gfni-rotates.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
    M llvm/test/CodeGen/X86/pr38539.ll
    M llvm/test/CodeGen/X86/pr62286.ll
    M llvm/test/CodeGen/X86/scheduler-backtracking.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
    M llvm/test/CodeGen/X86/vec_saddo.ll
    M llvm/test/CodeGen/X86/vec_ssubo.ll
    M llvm/test/CodeGen/X86/vec_uaddo.ll
    M llvm/test/CodeGen/X86/vec_usubo.ll
    M llvm/test/CodeGen/X86/vector-bo-select.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll

  Log Message:
  -----------
  Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more...

This reverts:
b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)"
(because it updates a test case that I don't know how to resolve the conflict for)
8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)"
73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)"

Due to a test suite failure on AArch64 when compiling for SVE.
https://lab.llvm.org/buildbot/#/builders/197/builds/13955

clang: ../llvm/llvm/include/llvm/CodeGen/ValueTypes.h:307: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications