[all-commits] [llvm/llvm-project] 8d49ce: [GlobalISel][AArch64] Add LLRINT support (#88702)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Apr 17 13:50:08 PDT 2024
Branch: refs/heads/users/alexey-bataev/spr/slpimprove-vectorization-of-gathered-loads
Home: https://github.com/llvm/llvm-project
Commit: 8d49ce176414cd4d0d5d276fd721d9226e17e810
https://github.com/llvm/llvm-project/commit/8d49ce176414cd4d0d5d276fd721d9226e17e810
Author: David Green <david.green at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter.td
Log Message:
-----------
[GlobalISel][AArch64] Add LLRINT support (#88702)
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint
nodes that already exist. On AArch64 they are treated the same as lrint
with the default return types.
Commit: 2c22a0c16d1cb844eac142156ba67098627a336c
https://github.com/llvm/llvm-project/commit/2c22a0c16d1cb844eac142156ba67098627a336c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/sub-xor.ll
Log Message:
-----------
[InstCombine] Add test case for turning sub into xor using dominating condition. NFC
I plan to disable using dominating conditions for turning sub into
xor, but first we need that demonstrates it currently happens.
Commit: 421a8c5892b7e59f27b2c21452f81fa789a758fd
https://github.com/llvm/llvm-project/commit/421a8c5892b7e59f27b2c21452f81fa789a758fd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
Log Message:
-----------
[InstCombine] Add phase ordering test for #88239. NFC
Commit: ed741ffe893698cd14c6785ac2ee7031d9d344a6
https://github.com/llvm/llvm-project/commit/ed741ffe893698cd14c6785ac2ee7031d9d344a6
Author: Nathan Lanza <nathanlanza at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[github] Add ClangIR to new-prs-labeler.yml (#86088)
Commit: c02ed29ec151d1d555c3735efef2ab215126ddbf
https://github.com/llvm/llvm-project/commit/c02ed29ec151d1d555c3735efef2ab215126ddbf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
Log Message:
-----------
[CostModel][X86] Recognise vector rotation by uniform constant patterns
Adds suitable costs for AVX512 targets (we still rely on default expansion for AVX2 and earlier)
Commit: 58a08e154c804051aaca9151a8053aea3ec15646
https://github.com/llvm/llvm-project/commit/58a08e154c804051aaca9151a8053aea3ec15646
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv32zba.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
Log Message:
-----------
[RISCV] Add coverage for strength reduction of mul by small negative immediates
Commit: cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
https://github.com/llvm/llvm-project/commit/cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
Author: Usman Nadeem <mnadeem at quicinc.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/load-insert-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/sat-add.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/sve-abd.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fcmp.ll
M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-arith.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
M llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-gep.ll
M llvm/test/CodeGen/AArch64/vselect-constants.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
Log Message:
-----------
[AArch64] Update latencies for Cortex-A510 scheduling model (#87293)
Updated according to the Software Optimization Guide for Arm®
Cortex®‑A510 Core Revision: r1p3 Issue 6.0.
Commit: 4572a2db2c2c48820e79fb65f3810348371db4f1
https://github.com/llvm/llvm-project/commit/4572a2db2c2c48820e79fb65f3810348371db4f1
Author: David Green <david.green at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll
Log Message:
-----------
[AArch64] Add some test cases for LD2/LD3/LD4 shuffles. NFC
Commit: 5a0942cd7423069e78fdfb9743a13aedfa7bdee0
https://github.com/llvm/llvm-project/commit/5a0942cd7423069e78fdfb9743a13aedfa7bdee0
Author: Youngsuk Kim <joseph942010 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[llvm][NVPTX] Don't emit unused var 'temp_param_reg' (NFC) (#89004)
Don't emit unused variable 'temp_param_reg' which has been around since
ae556d3ef72dfe5f40a337b7071f42b7bf5b66a4 .
Commit: 800f1050e190430f217e1fd0db9414dacc835e11
https://github.com/llvm/llvm-project/commit/800f1050e190430f217e1fd0db9414dacc835e11
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[GitHub] Add a new mapping for `offload` subproject (#89118)
Fix #89071.
Commit: 6f7976c883da592f2cf6bfadef152e4203c00445
https://github.com/llvm/llvm-project/commit/6f7976c883da592f2cf6bfadef152e4203c00445
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libcxx/docs/Status/FormatPaper.csv
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/sys_info.h
M libcxx/include/chrono
A libcxx/test/libcxx/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
A libcxx/test/std/time/time.syn/formatter.sys_info.pass.cpp
A libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/support/test_macros.h
Log Message:
-----------
[libc++][TZDB] Adds sys_info formatter. (#85896)
Implements parts of:
- P0355 Extending <chrono> to Calendars and Time Zones
- P1361 Integration of chrono with text formatting
Commit: b1dc62f139ef265a36a2a739ce9ba4e1e48a6dbe
https://github.com/llvm/llvm-project/commit/b1dc62f139ef265a36a2a739ce9ba4e1e48a6dbe
Author: Amirreza Ashouri <ar.ashouri999 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/lib/Parse/ParseExprCXX.cpp
M clang/test/Sema/static-assert.c
M clang/test/SemaCXX/builtins.cpp
M clang/test/SemaCXX/deprecated-builtins.cpp
Log Message:
-----------
[clang]Treat arguments to builtin type traits as template type arguments (#87132)
This change improves error messages for builtins in case of empty
parentheses.
Fixes llvm#86997
Commit: 6cea7c491f4c4c68aa0494a9b18f36ff40c22c81
https://github.com/llvm/llvm-project/commit/6cea7c491f4c4c68aa0494a9b18f36ff40c22c81
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/test/CodeGen/X86/code-model-elf.ll
Log Message:
-----------
[X86] Always use 64-bit relocations in no-PIC large code model (#89101)
This matches other types of relocations, e.g. to constant pool. And
makes things more consistent with PIC large code model.
Some users of the large code model may not place small data in the lower
2GB of the address space (e.g.
https://github.com/ClangBuiltLinux/linux/issues/2016), so just
unconditionally use 64-bit relocations in the large code model.
So now functions in a section not marked large will use 64-bit
relocations to reference everything when using the large code model.
This also fixes some lldb tests broken by #88172
(https://lab.llvm.org/buildbot/#/builders/68/builds/72458).
Commit: 1460b4964c7ada2f7536006722c8585b5bd0a1b5
https://github.com/llvm/llvm-project/commit/1460b4964c7ada2f7536006722c8585b5bd0a1b5
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Manually port d423d80e560d
Commit: db2f64ee1f743153f242ca92bf627458ba7f8000
https://github.com/llvm/llvm-project/commit/db2f64ee1f743153f242ca92bf627458ba7f8000
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
Log Message:
-----------
AMDGPU: Fix not handling atomicrmw fadd in exotic address spaces correctly
We try to interpret unknown address space numbers as aliases of global,
but this wasn't applied here. Also improve test coverage for the
buffer fat pointer address space.
Commit: 652bcf685c72447f3cc46d93d6c9c1948e8499f3
https://github.com/llvm/llvm-project/commit/652bcf685c72447f3cc46d93d6c9c1948e8499f3
Author: Matthias Braun <matze at braunis.de>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
A llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
A llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-tls.ll
Log Message:
-----------
CodeGenPrepare: Add support for llvm.threadlocal.address address-mode sinking (#87844)
Depending on the TLSMode many thread-local accesses on x86 can be
expressed by adding a %fs: segment register to an addressing mode. Even
if there are mutliple users of a `llvm.threadlocal.address` intrinsic it
is generally not worth sharing the value in a register but instead fold
the %fs access into multiple addressing modes.
Hence this changes CodeGenPrepare to duplicate the
`llvm.threadlocal.address` intrinsic as necessary.
Introduces a new `TargetLowering::addressingModeSupportsTLS` callback
that allows targets to indicate whether TLS accesses can be part of an
addressing mode.
This is fixing a performance problem, as this folding of TLS-accesses
into multiple addressing modes happened naturally before the
introduction of the `llvm.threadlocal.address` intrinsic, but regressed
due to `SelectionDAG` keeping things in registers when accessed across
basic blocks, so CodeGenPrepare needs to duplicate to mitigate this. We
see a ~0.5% recovery in a codebase with heavy TLS usage (HHVM).
This fixes most of #87437
Commit: 2583b2eea4a509424e5e5f51dffedd9beede76a3
https://github.com/llvm/llvm-project/commit/2583b2eea4a509424e5e5f51dffedd9beede76a3
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/runtime/extensions.cpp
Log Message:
-----------
[flang][NFC] Add missing include for FreeBSD
Suggested by dankm here: https://github.com/llvm/llvm-project/pull/88517
Commit: 7af09fba150c92a35e8644d8557c1acf73b82ad8
https://github.com/llvm/llvm-project/commit/7af09fba150c92a35e8644d8557c1acf73b82ad8
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
M clang/lib/Parse/ParseExprCXX.cpp
M clang/test/Sema/static-assert.c
M clang/test/SemaCXX/builtins.cpp
M clang/test/SemaCXX/deprecated-builtins.cpp
M flang/runtime/extensions.cpp
M libcxx/docs/Status/FormatPaper.csv
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/sys_info.h
M libcxx/include/chrono
A libcxx/test/libcxx/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
A libcxx/test/std/time/time.syn/formatter.sys_info.pass.cpp
A libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/support/test_macros.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/load-insert-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/sat-add.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/sve-abd.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fcmp.ll
M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-arith.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
M llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-gep.ll
M llvm/test/CodeGen/AArch64/vselect-constants.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/RISCV/rv32zba.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
M llvm/test/CodeGen/X86/code-model-elf.ll
A llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
A llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-tls.ll
M llvm/test/Transforms/InstCombine/sub-xor.ll
A llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
Fix formatting
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/00d7fe551ea4...7af09fba150c
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