[all-commits] [llvm/llvm-project] 65b0cc: [RISCV] Add FeatureStdExtI to all CPUs in RISCVPro...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799
      https://github.com/llvm/llvm-project/commit/65b0cc610f80d9b9724a98cf7c5bcfd38e1cf799
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add FeatureStdExtI to all CPUs in RISCVProcessors.td. NFC (#88805)

This is currently being implied in RISCVISAInfo.cpp. Make it explicit.

I'm planning to move all extension information to RISCVFeatures.td and
have tablegen create the tables for RISCVISAInfo.cpp. This requires
making the creation of RISCVTargetParserDef.inc in tablegen independent
of RISCVISAInfo.cpp. So we need an accurate extension list for CPUs in
tablegen.



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