[all-commits] [llvm/llvm-project] 5fa58e: [RISCV] Split PseudoVFADD, PseudoVFSUB, and Pseudo...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fa58e28f34f4b5b41dd2869212ac917fb42b2e3
      https://github.com/llvm/llvm-project/commit/5fa58e28f34f4b5b41dd2869212ac917fb42b2e3
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split PseudoVFADD, PseudoVFSUB, and PseudoVFRSUB by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


  Commit: aece68269c8cb28e16dc5c4ec9aabecb807a0438
      https://github.com/llvm/llvm-project/commit/aece68269c8cb28e16dc5c4ec9aabecb807a0438
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split PseudoVFWADD, PseudoVFWSUB, and PseudoVFWMUL by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


  Commit: d309d7e4fe51a0ff0ce6430a8af585e2af2772a3
      https://github.com/llvm/llvm-project/commit/d309d7e4fe51a0ff0ce6430a8af585e2af2772a3
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split PseudoVFMUL by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


  Commit: c6b7944be4dfbb1fb35301c670812726845acaa7
      https://github.com/llvm/llvm-project/commit/c6b7944be4dfbb1fb35301c670812726845acaa7
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split single width floating point fused multiple-add pseudo instructions by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


  Commit: 43248ffea7b8de3a33b11768e8c21d2434252528
      https://github.com/llvm/llvm-project/commit/43248ffea7b8de3a33b11768e8c21d2434252528
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll
    M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll

  Log Message:
  -----------
  [RISCV] Split widening floating point fused multiple-add pseudo instructions by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


  Commit: b8e1ff322104e5445371328a4fbc9c1d2bf82f01
      https://github.com/llvm/llvm-project/commit/b8e1ff322104e5445371328a4fbc9c1d2bf82f01
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-12 (Fri, 12 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Split PseudoVFRSQRT7 and PseudoVFREC7 by SEW

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>


Compare: https://github.com/llvm/llvm-project/compare/2a5ba4fb8959...b8e1ff322104

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