[all-commits] [llvm/llvm-project] f5b2d2: [NVPTX] Move roundeven on bf16 into the sm_90 has ...
Sergio Afonso via All-commits
all-commits at lists.llvm.org
Fri Apr 12 03:59:51 PDT 2024
Branch: refs/heads/users/skatrak/spr/clause-operands-02-flang
Home: https://github.com/llvm/llvm-project
Commit: f5b2d24b59f168eaeed08b5f45bf0c8dfcc1c292
https://github.com/llvm/llvm-project/commit/f5b2d24b59f168eaeed08b5f45bf0c8dfcc1c292
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-04-12 (Fri, 12 Apr 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
Log Message:
-----------
[NVPTX] Move roundeven on bf16 into the sm_90 has it but sm_80 doesn't bucket
Commit: b24af43fdfa1b1242b7cb77540462212227c57c4
https://github.com/llvm/llvm-project/commit/b24af43fdfa1b1242b7cb77540462212227c57c4
Author: David Green <david.green at arm.com>
Date: 2024-04-12 (Fri, 12 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Hexagon/HexagonSubtarget.h
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
Log Message:
-----------
[AArch64] Improve scheduling latency into Bundles (#86310)
By default the scheduling info of instructions into a BUNDLE are given a
latency of 0 as they operate on the implicit register of the bundle.
This modifies that for AArch64 so that the latency is adjusted to use
the latency from the instruction in the bundle instead. This essentially
assumes that the bundled instructions are executed in a single cycle,
which for AArch64 is probably OK considering they are mostly used for
MOVPFX bundles, where this can help create slightly better scheduling
especially for in-order cores.
Commit: 5fc8a190b37906cba3f175440abd79dabd8acc73
https://github.com/llvm/llvm-project/commit/5fc8a190b37906cba3f175440abd79dabd8acc73
Author: wanglei <wanglei at loongson.cn>
Date: 2024-04-12 (Fri, 12 Apr 2024)
Changed paths:
A llvm/test/Transforms/CodeGenPrepare/LoongArch/lit.local.cfg
A llvm/test/Transforms/CodeGenPrepare/LoongArch/splitgep.ll
Log Message:
-----------
[LoongArch] Pre commit test for #88371. NFC
Commit: f3b7583dd7450d7444900bfcf76dc8e52ef55d3a
https://github.com/llvm/llvm-project/commit/f3b7583dd7450d7444900bfcf76dc8e52ef55d3a
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-12 (Fri, 12 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Hexagon/HexagonSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
A llvm/test/Transforms/CodeGenPrepare/LoongArch/lit.local.cfg
A llvm/test/Transforms/CodeGenPrepare/LoongArch/splitgep.ll
Log Message:
-----------
Merge branch 'main' into users/skatrak/spr/clause-operands-02-flang
Compare: https://github.com/llvm/llvm-project/compare/ffc0ccd2212e...f3b7583dd745
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