[all-commits] [llvm/llvm-project] 4e98ad: [RISCV] Add tests for F/D with non-FP ABI to inter...
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Tue Apr 9 09:23:51 PDT 2024
Branch: refs/heads/users/arichardson/spr/memprof-use-compiler_rt_test_compiler
Home: https://github.com/llvm/llvm-project
Commit: 4e98adf677fe6eb9aea5606c44ccc97f02d2f48a
https://github.com/llvm/llvm-project/commit/4e98adf677fe6eb9aea5606c44ccc97f02d2f48a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
Log Message:
-----------
[RISCV] Add tests for F/D with non-FP ABI to interrupt-attr.ll. NFC
Without a floating point aware ABI for callees, an interrupt handler
needs to save all floating point registers even normally callee saved.
We are currently unnecessarily saving callee saved FP registers when
a floating point ABI is used by the callee. This is different than gcc
as noted in this discourse
post https://discourse.llvm.org/t/has-bugs-when-optimizing-save-restore-csrs-by-changing-csr-xlen-f32-interrupt/78200/1
Commit: 79343fa8c3575be12ec4d543f4aebebd1ba4f47f
https://github.com/llvm/llvm-project/commit/79343fa8c3575be12ec4d543f4aebebd1ba4f47f
Author: Evgenii Stepanov <eugenis at google.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
A llvm/test/Instrumentation/MemorySanitizer/overflow.ll
A llvm/test/Instrumentation/MemorySanitizer/saturating.ll
Log Message:
-----------
[msan] Precommit tests.
Precommit tests for overflowing and saturating arithmetic intrinsics.
Commit: 22b1f1bc695b8fd3263b709ce9761bf3bb2f8ee9
https://github.com/llvm/llvm-project/commit/22b1f1bc695b8fd3263b709ce9761bf3bb2f8ee9
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M libc/include/llvm-libc-macros/math-macros.h
Log Message:
-----------
[libc] Remove `#ifdef __cplusplus` part from `include/llvm-libc-macros/math-macros.h`. (#87864)
Now with the proxy header `hdr/math_macros.h`, the header
`include/llvm-libc-macros/math-macros.h` will not be included in overlay
mode, and the extra definitions for `__cplusplus` mode is not needed any
more.
Commit: 118a5d8236d8a483dd401fa35c8b1fcd058eacc1
https://github.com/llvm/llvm-project/commit/118a5d8236d8a483dd401fa35c8b1fcd058eacc1
Author: Evgenii Stepanov <eugeni.stepanov at gmail.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/overflow.ll
M llvm/test/Instrumentation/MemorySanitizer/saturating.ll
Log Message:
-----------
Overflow and saturating intrinsics (#88068)
Commit: f28c8339c12917b11c99432de6609e7d46e17e2b
https://github.com/llvm/llvm-project/commit/f28c8339c12917b11c99432de6609e7d46e17e2b
Author: Chris Apple <cja-private at pm.me>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M compiler-rt/cmake/config-ix.cmake
Log Message:
-----------
Fix issue where MACOSX_VERSION_MIN_FLAG was not set on subsequent runs of CMake in compiler-rt (#87580)
As discussed here:
https://github.com/llvm/llvm-project/pull/74394#issuecomment-2035264683
An unintentional change of behavior was introduced in #74394
This code introduced in #74394 :
The first time through
* SANITIZER_MIN_OSX_VERSION is not set
* parse -mmacosx-version-min and set MACOSX_VERSION_MIN_FLAG
* Set and cache SANITIZER_MIN_OSX_VERSION
Subsequent times through:
* SANITIZER_MIN_OSX_VERSION is cached
* (BUG!!) you don't parse -mmacosx-version-min, and don't set
MACOSX_VERSION_MIN_FLAG
MACOSX_VERSION_MIN_FLAG is used later in the file on this line:
https://github.com/llvm/llvm-project/blob/63c925ca808f216f805b76873743450456e350f2/compiler-rt/cmake/config-ix.cmake#L517
Hoisting this assignment outside the if block returns us to the previous
behavior before this commit, while maintaining the flexibility
introduced with the cache variable
Commit: ccdebbae4d77d3efc236af92c22941de5d437e01
https://github.com/llvm/llvm-project/commit/ccdebbae4d77d3efc236af92c22941de5d437e01
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/arm-compiler-rt.c
M clang/test/Driver/cl-link.c
M clang/test/Driver/compiler-rt-unwind.c
M clang/test/Driver/coverage-ld.c
M clang/test/Driver/instrprof-ld.c
M clang/test/Driver/linux-ld.c
M clang/test/Driver/mingw-sanitizers.c
M clang/test/Driver/msp430-toolchain.c
M clang/test/Driver/print-libgcc-file-name-clangrt.c
M clang/test/Driver/print-runtime-dir.c
M clang/test/Driver/riscv32-toolchain-extra.c
M clang/test/Driver/riscv32-toolchain.c
M clang/test/Driver/riscv64-toolchain-extra.c
M clang/test/Driver/riscv64-toolchain.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Driver/wasm-toolchain.c
M clang/test/Driver/wasm-toolchain.cpp
M clang/test/Driver/windows-cross.c
M clang/test/Driver/zos-ld.c
M flang/test/Driver/msvc-dependent-lib-flags.f90
Log Message:
-----------
[Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin
Follow-up to #81037.
ToolChain::LibraryPaths holds the new compiler-rt library directory
(e.g. `/tmp/Debug/lib/clang/19/lib/x86_64-unknown-linux-gnu`). However,
it might be empty when the directory does not exist (due to the `if
(getVFS().exists(P))` change in https://reviews.llvm.org/D158475).
If neither the old/new compiler-rt library directories exists, we would
suggest the undesired old compiler-rt file name:
```
% /tmp/Debug/bin/clang++ a.cc -fsanitize=memory -o a
ld.lld: error: cannot open /tmp/Debug/lib/clang/19/lib/linux/libclang_rt.msan-x86_64.a: No such file or directory
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
```
With this change, we will correctly suggest the new compiler-rt file name.
Fix #87150
Pull Request: https://github.com/llvm/llvm-project/pull/87866
Commit: ec1af63dde58c735fe60d6f2aafdb10fa93f410d
https://github.com/llvm/llvm-project/commit/ec1af63dde58c735fe60d6f2aafdb10fa93f410d
Author: Alexandre Ganea <37383324+aganea at users.noreply.github.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/patchable-prologue.ll
Log Message:
-----------
[Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639)
This fixes an edge case where functions starting with inline assembly
would assert while trying to lower that inline asm instruction.
After this PR, for now we always add a no-op (xchgw in this case) without
considering the size of the next inline asm instruction. We might want
to revisit this in the future.
This fixes Unreal Engine 5.3.2 compilation with clang-cl and /HOTPATCH.
Should close https://github.com/llvm/llvm-project/issues/56234
Commit: 5bc87dac75762027e614da31b968c67a94f0e7b1
https://github.com/llvm/llvm-project/commit/5bc87dac75762027e614da31b968c67a94f0e7b1
Author: Evgenii Stepanov <eugenis at google.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/overflow.ll
M llvm/test/Instrumentation/MemorySanitizer/saturating.ll
Log Message:
-----------
Revert "Overflow and saturating intrinsics (#88068)"
This reverts commit 118a5d8236d8a483dd401fa35c8b1fcd058eacc1.
Commit: 3b74f8c1de72aa90445249f55923690301da024a
https://github.com/llvm/llvm-project/commit/3b74f8c1de72aa90445249f55923690301da024a
Author: Evgenii Stepanov <eugenis at google.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
R llvm/test/Instrumentation/MemorySanitizer/overflow.ll
R llvm/test/Instrumentation/MemorySanitizer/saturating.ll
Log Message:
-----------
Revert "[msan] Precommit tests."
This reverts commit 79343fa8c3575be12ec4d543f4aebebd1ba4f47f.
Commit: be006372f3bbcab1e2e51af93dd3302398dac9a4
https://github.com/llvm/llvm-project/commit/be006372f3bbcab1e2e51af93dd3302398dac9a4
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/AsmPrinter.cpp
Log Message:
-----------
[mlir][OpPrintingFlags] Allow to disable ElementsAttr hex printing (#85766)
At present, large ElementsAttr is unconditionally printed with a hex
string. This means that in IR large constant values often look like:
dense<"0x000000000004000000080000000004000000080000000..."> :
tensor<10x10xi32>
Hoisting hex printing control to the user level for tooling means that
one can disable the feature and get human-readable values when
necessary:
dense<[16, 32, 48, 500...]> : tensor<10x10xi32>
Note: AsmPrinterOptions::printElementsAttrWithHexIfLarger is not always
possible to be used as it requires that one exposes MLIR's command-line
options in user tooling (including an actual compiler).
Co-authored-by: Harald Rotuna <harald.razvan.rotuna at intel.com>
Commit: b2f8172d721d9e1cdaf052155aea880d731b1bf7
https://github.com/llvm/llvm-project/commit/b2f8172d721d9e1cdaf052155aea880d731b1bf7
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn
Log Message:
-----------
[gn build] Port 27b2d7d4bb79
Commit: 65c57bf2429e395aed811c05f35d28a6123a5965
https://github.com/llvm/llvm-project/commit/65c57bf2429e395aed811c05f35d28a6123a5965
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn
Log Message:
-----------
[gn build] Port 7a4e89761a13
Commit: 1c4ec8def6bb18934f300f6e630e92e7efdb60be
https://github.com/llvm/llvm-project/commit/1c4ec8def6bb18934f300f6e630e92e7efdb60be
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
Log Message:
-----------
[gn build] Port d2884444472e
Commit: 064634406277e4786ce12caac94f7fa57ed5973e
https://github.com/llvm/llvm-project/commit/064634406277e4786ce12caac94f7fa57ed5973e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
M llvm/test/Transforms/lower-builtin-allow-check.ll
Log Message:
-----------
[HWASAN][UBSAN] Reverse random logic (#88070)
It feels more intuitive to make higher P to keep more checks.
Commit: 4a812b5912d3149592cae195c9007b05649d9b41
https://github.com/llvm/llvm-project/commit/4a812b5912d3149592cae195c9007b05649d9b41
Author: Matthias Braun <matze at braunis.de>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/lib/IR/Verifier.cpp
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
Verify threadlocal_address constraints (#87841)
Check invariants for `llvm.threadlocal.address` intrinsic in IR
Verifier.
Commit: 925b7d6f62bf8f0b204cc1cb24a4a75c7bc5e0ae
https://github.com/llvm/llvm-project/commit/925b7d6f62bf8f0b204cc1cb24a4a75c7bc5e0ae
Author: Lang Hames <lhames at gmail.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Replace some KV loop variables with structured bindings.
Same idea as 006aaf32258 -- reduce boilerplate and improve readability. This
time updates will be piecemeal to make it easier to identify errors.
Coding my way home: 2.18555S, 93.78063W
Commit: e35fb3fb8bfcb732ace3738f9589989b3fac1508
https://github.com/llvm/llvm-project/commit/e35fb3fb8bfcb732ace3738f9589989b3fac1508
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i
M lldb/bindings/interface/SBProcessDocstrings.i
M lldb/bindings/interface/SBQueueDocstrings.i
M lldb/bindings/interface/SBThreadDocstrings.i
Log Message:
-----------
[lldb] [NFC] Fix swig docstring annotations (#88073)
Some of the SB API method description docstrings for swing are annotated
as `%feature("autodoc")` - but `"autodoc"` annotations are only to
substitute a string showing the arguments and return variables - either
in a single line, or in multiple lines. SBMemoryRegionInfo used
`"autodoc"` correctly describing the parameters and return type, but
then it added a description too which is not correct either.
Change all of these that are adding a method description to use
`%feature("docstring")` instead. There were a half dozen instances where
`"autodoc"` was correctly being used and we have overriden the parameter
and return types with a more readable version.
Commit: f7d93373969b2b757f5d5ef5e157dabe3bb9b0ae
https://github.com/llvm/llvm-project/commit/f7d93373969b2b757f5d5ef5e157dabe3bb9b0ae
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Log Message:
-----------
[Sema][NFC] Cleanups after 843cc474f (#87996)
I forgot to tidy up these lines that should've been done in the previous
commit, specifically:
1. Merge two `CodeSynthesisContext`s into one in `CheckTemplateIdType`.
2. Remove some gratuitous `Sema::` specifiers.
3. Rename the parameter `Template` to `Entity` to avoid confusion.
Commit: 41dc04e5283adef9979cad2b126ab3e6c156034a
https://github.com/llvm/llvm-project/commit/41dc04e5283adef9979cad2b126ab3e6c156034a
Author: Jason Molenda <jason at molenda.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M lldb/bindings/interface/SBProcessDocstrings.i
Log Message:
-----------
[lldb] Add swig doc for SBProcess address mask methods
Add descriptions of `GetAddressMask`, `SetAddressMask`,
`SetAddressableBits`, and `FixAddress` SBProcess methods.
Commit: 71eda17a0674317b05975be79ed4a2c8ee99c43c
https://github.com/llvm/llvm-project/commit/71eda17a0674317b05975be79ed4a2c8ee99c43c
Author: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/test/CodeGen/PowerPC/ppcsoftops.ll
Log Message:
-----------
[Legalizer] Soften EXTRACT_ELEMENT on ppcf128 (#77412)
ppc_fp128 values are always split into two f64. Implement soften
operation in soft-float mode to handle output f64 correctly.
Commit: 0e5a53cc01e406436cb7c703c84598e474d635de
https://github.com/llvm/llvm-project/commit/0e5a53cc01e406436cb7c703c84598e474d635de
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M mlir/include/mlir/IR/AffineExprVisitor.h
M mlir/test/IR/affine-walk.mlir
Log Message:
-----------
[MLIR] Fix typo bug in AffineExprVisitor for WalkResult return case (#86138)
Fix typo bug in AffineExprVisitor for the WalkResult return case. This
didn't show up immmediately because most walks in the tree didn't
use walk result.
Commit: 25e3d2b0fc1e2b4df19d7f18fbdd04c154e1d0e8
https://github.com/llvm/llvm-project/commit/25e3d2b0fc1e2b4df19d7f18fbdd04c154e1d0e8
Author: Pete Steinfeld <47540744+psteinfeld at users.noreply.github.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M clang/test/Headers/Inputs/include/stdint.h
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
Revert "[Libomp] Place generated OpenMP headers into build resource d… (#88083)
…irectory (#88007)"
This reverts commit 8671429151d5e67d3f21a737809953ae8bdfbfde.
This commit broke the flang build, so I'm reverting it. See the comments
in merge request #88007 for more information.
Commit: 74c085fcfc8fab7822127cb46ff82a6f0d3597f3
https://github.com/llvm/llvm-project/commit/74c085fcfc8fab7822127cb46ff82a6f0d3597f3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[RISCV] Add Zcmop and Zimop to RISCVUsage.rst. NFC (#88033)
These extensions are ratified so they were removed from the experimental
section, but not added to the non-experimental section.
Commit: 04f33a3ac2e8ca96840606f812eaef974ff61c80
https://github.com/llvm/llvm-project/commit/04f33a3ac2e8ca96840606f812eaef974ff61c80
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[APInt] Use a std::move() to avoid a copy in the loop in multiplicativeInverse. (#87655)
This allows the subtract to reuse the storage of T. T will be assigned
over by the condition on the next iteration. I think assigning over a
moved from value should be ok.
Commit: a30662fc2acdd73ca1a9217716299a4676999fb4
https://github.com/llvm/llvm-project/commit/a30662fc2acdd73ca1a9217716299a4676999fb4
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/test/AST/ast-print-method-decl.cpp
M clang/test/AST/ast-print-no-sanitize.cpp
M clang/test/AST/attr-print-emit.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/OpenMP/assumes_codegen.cpp
M clang/test/OpenMP/assumes_print.cpp
M clang/test/OpenMP/assumes_template_print.cpp
M clang/test/OpenMP/declare_simd_ast_print.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/cxx11-attr-print.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
Rework the printing of attributes (#87281)
Commit https://github.com/llvm/llvm-project/commit/46f3ade introduced a
notion of printing the attributes on the left to improve the printing of
attributes attached to variable declarations. The intent was to produce
more GCC compatible code because clang tends to print the attributes on
the right hand side which is not accepted by gcc.
This approach has increased the complexity in tablegen and the
attrubutes themselves as now the are supposed to know where they could
appear. That lead to mishandling of the `override` keyword which is
modelled as an attribute in clang.
This patch takes an inspiration from the existing approach and tries to
keep the position of the attributes as they were written. To do so we
use simpler heuristic which checks if the source locations of the
attribute precedes the declaration. If so, it is considered to be
printed before the declaration.
Fixes https://github.com/llvm/llvm-project/issues/87151
Commit: 5c056b32350e834924356b1af78504d261d24e42
https://github.com/llvm/llvm-project/commit/5c056b32350e834924356b1af78504d261d24e42
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Clean up unit tests from commit 13be0d4a34c4
- Use 1-parameter verifyFormat() to verify formatted input in LLVM style.
- Pass string literal instead of constructed StringRef to verifyFormat().
- Don't include trailing newlines if not needed.
Commit: b65ab0b726ce421cc6cd7fdfbf51bf4aba17ce87
https://github.com/llvm/llvm-project/commit/b65ab0b726ce421cc6cd7fdfbf51bf4aba17ce87
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
Log Message:
-----------
[ValueTracking] Add comment clarifying missing `usub.sat` in `isKnownNonZero`; NFC
Closes #87700
Commit: d10983b8a39abdbfaffd207720f67f96227b5ac9
https://github.com/llvm/llvm-project/commit/d10983b8a39abdbfaffd207720f67f96227b5ac9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-04-08 (Mon, 08 Apr 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
Log Message:
-----------
[ORC] Replace KV loop variables with structured bindings, fix typo.
Coding my way home: 2.29247S, 94.15173W
Commit: 62e92573d28d62ab7e6438ac34d513b07c51ce09
https://github.com/llvm/llvm-project/commit/62e92573d28d62ab7e6438ac34d513b07c51ce09
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/test/AST/ast-print-method-decl.cpp
M clang/test/AST/ast-print-no-sanitize.cpp
M clang/test/AST/attr-print-emit.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/OpenMP/assumes_codegen.cpp
M clang/test/OpenMP/assumes_print.cpp
M clang/test/OpenMP/assumes_template_print.cpp
M clang/test/OpenMP/declare_simd_ast_print.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/cxx11-attr-print.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
Revert "Rework the printing of attributes (#87281)"
This reverts commit a30662fc2acdd73ca1a9217716299a4676999fb4 due to bot failures.
Commit: d4120477130a5f9e472753068dcc627baddc44f6
https://github.com/llvm/llvm-project/commit/d4120477130a5f9e472753068dcc627baddc44f6
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/Pointer.cpp
M clang/test/AST/Interp/arrays.cpp
Log Message:
-----------
[clang][Interp] Fix "Initializing" zero-size arrays
getIndex() returns 0 here, so we were trying to initalize the 0th
element.
Fixes #88018
Commit: 03ffb82c9e0d363c97ca37ede46719236616c88e
https://github.com/llvm/llvm-project/commit/03ffb82c9e0d363c97ca37ede46719236616c88e
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/include/llvm/Support/ToolOutputFile.h
M llvm/lib/Support/ToolOutputFile.cpp
Log Message:
-----------
[Support] Make CleanupInstaller public (NFC) (#86758)
This can be used by others to automatically remove temp files.
Commit: c7db450e5c1a83ea768765dcdedfd50f3358d418
https://github.com/llvm/llvm-project/commit/c7db450e5c1a83ea768765dcdedfd50f3358d418
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/Sema/SemaExprCXX.cpp
Log Message:
-----------
[clang][NFC] Refactor `EvaluateBinaryTypeTrait` to accept `TypeSourceInfo`
Some type traits issue diagnostics that would benefit from additional source location information.
Commit: 5d1f779540517f47abb4927f4ded51cac94fd366
https://github.com/llvm/llvm-project/commit/5d1f779540517f47abb4927f4ded51cac94fd366
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
Log Message:
-----------
[clang][Interp][NFC] Add Dump debug op
This is often useful for debugging and dumps the current stack
contents.
Commit: acff0b03167f877f783d9386014e1ebc20db1c2f
https://github.com/llvm/llvm-project/commit/acff0b03167f877f783d9386014e1ebc20db1c2f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/Disasm.cpp
M clang/lib/AST/Interp/Record.cpp
M clang/lib/AST/Interp/Record.h
Log Message:
-----------
[clang][Interp][NFC] Improve Record debugging
Add Record::dump() and return the diagnostic name from getName()
Commit: 11ba795565c231a95a7e34bb0e4dff099234c736
https://github.com/llvm/llvm-project/commit/11ba795565c231a95a7e34bb0e4dff099234c736
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
Log Message:
-----------
[clang][Interp][NFC] Add sanity checks to This op
The instance pointer must be casted to the right base.
Commit: 3a2367561d7f4eb1795d6972b294562bc66beb2b
https://github.com/llvm/llvm-project/commit/3a2367561d7f4eb1795d6972b294562bc66beb2b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/insertelement.ll
Log Message:
-----------
[ValueTracking] Add tests for non-constant idx in `computeKnownBits` of `insertelement`; NFC
Commit: 964df099e1f8afcb9d052f61e065da82b19cc81b
https://github.com/llvm/llvm-project/commit/964df099e1f8afcb9d052f61e065da82b19cc81b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/insertelement.ll
Log Message:
-----------
[ValueTracking] Support non-constant idx for `computeKnownBits` of `insertelement`
Its same logic as before, we just need to intersect what we know about
the new Elt and the entire pre-existing Vec.
Closes #87707
Commit: 51089e360e37962c7841fe0a494ba9fb5368bab2
https://github.com/llvm/llvm-project/commit/51089e360e37962c7841fe0a494ba9fb5368bab2
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[mlir][complex] Support fast math flag for complex.tan op (#87919)
See
https://discourse.llvm.org/t/rfc-fastmath-flags-support-in-complex-dialect/71981
Commit: dbb9749862481ad6aa82c96f6889b2ebba6f6062
https://github.com/llvm/llvm-project/commit/dbb9749862481ad6aa82c96f6889b2ebba6f6062
Author: Ding Fei <fding at feysh.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
Log Message:
-----------
[ASTMatchers] fix captureVars assertion failure on capturesVariables (#76619)
Matcher `capturesVar` should check for `capturesVariables()` before
calling `getCaptureVar()` since it asserts this `LambdaCapture` does
capture a variable.
Fixes #76425
Commit: 9391ff8c86007562d40c240ea082b7c0cbf35947
https://github.com/llvm/llvm-project/commit/9391ff8c86007562d40c240ea082b7c0cbf35947
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/test/APINotes/retain-count-convention.m
M clang/test/APINotes/versioned.m
M clang/test/AST/ast-print-method-decl.cpp
M clang/test/AST/ast-print-no-sanitize.cpp
M clang/test/AST/attr-print-emit.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/OpenMP/assumes_codegen.cpp
M clang/test/OpenMP/assumes_print.cpp
M clang/test/OpenMP/assumes_template_print.cpp
M clang/test/OpenMP/declare_simd_ast_print.cpp
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/cxx11-attr-print.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
Reland "Rework the printing of attributes (#87281)"
Original commit message:
"
Commit https://github.com/llvm/llvm-project/commit/46f3ade introduced a notion
of printing the attributes on the left to improve the printing of attributes
attached to variable declarations. The intent was to produce more GCC compatible
code because clang tends to print the attributes on the right hand side which is
not accepted by gcc.
This approach has increased the complexity in tablegen and the attrubutes
themselves as now the are supposed to know where they could appear. That lead to
mishandling of the `override` keyword which is modelled as an attribute in
clang.
This patch takes an inspiration from the existing approach and tries to keep the
position of the attributes as they were written. To do so we use simpler
heuristic which checks if the source locations of the attribute precedes the
declaration. If so, it is considered to be printed before the declaration.
Fixes https://github.com/llvm/llvm-project/issues/87151
"
The reason for the bot breakage is that attributes coming from ApiNotes are not
marked implicit even though they do not have source locations. This caused an
assert to trigger. This patch forces attributes with no source location
information to be printed on the left. That change is consistent to the overall
intent of the change to increase the chances for attributes to compile across
toolchains and at the same time the produced code to be as close as possible to
the one written by the user.
Commit: d8d131dfa99762ccdd2116661980b7d0493cd7b5
https://github.com/llvm/llvm-project/commit/d8d131dfa99762ccdd2116661980b7d0493cd7b5
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
Log Message:
-----------
[RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616)
A handy shorthand for specifying the shufflevector(insertelement(poison,
foo, 0), poison, zeroinitializer) splat pattern was introduced in
#74620.
Some of the RISC-V tests were converted over to use this new form in
dbb65dd330cc1696d7ca3dedc7aa9fa12c55a075, this patch handles the rest
which didn't have any codegen diffs.
This not only converts some constant expressions to the new form, but
also instruction sequences that weren't previously constant expressions
to constant expressions as well. In some cases this affects codegen, but
these have been omitted here and will be handled in a separate PR.
Commit: 0f20b9b92f5333a90cf7cd19d7ec2e27ee3eac06
https://github.com/llvm/llvm-project/commit/0f20b9b92f5333a90cf7cd19d7ec2e27ee3eac06
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
Log Message:
-----------
[RISCV] Don't require mask or VL to be the same in combineBinOp_VLToVWBinOp_VL (#87997)
In NodeExtensionHelper we keep track of the VL and mask of the operand
being extended and check that they are the same as the root node's.
However for the nodes that we support, none of them have a passthru
operand with the exception of RISCV::VMV_V_X_VL, but we check that it's
passthru is undef anyway.
So it's safe to just discard the extend node's VL and mask and just use
the root's instead. (This is the same type of reasoning we use to treat
any vmset_vl as an all ones mask)
This allows us to match some more cases where we mix VP/non-VP/VL nodes,
but these don't seem to appear in practice. The main benefit from this
would be to simplify the code.
Commit: 9c660362c4fb05c0198b9d3ed65b2344706129bd
https://github.com/llvm/llvm-project/commit/9c660362c4fb05c0198b9d3ed65b2344706129bd
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
Log Message:
-----------
[RISCV] Support vwsll in combineBinOp_VLToVWBinOp_VL (#87620)
If the subtarget has +zvbb then we can attempt folding shl and shl_vl to
vwsll nodes.
There are few test cases where we still don't pick up the vwsll:
- For fixed vector vwsll.vi on RV32, see the FIXME for VMV_V_X_VL in
fillUpExtensionSupport for support implicit sign extension
- For scalable vector vwsll.vi we need to support ISD::SPLAT_VECTOR, see
#87249
Commit: 9c58f3a234a5eb24db97290d1abc71f8bf181c3a
https://github.com/llvm/llvm-project/commit/9c58f3a234a5eb24db97290d1abc71f8bf181c3a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
Log Message:
-----------
[AMDGPU] Fix implicit $vcc operands after parsing MIR (#87781)
MIParser checks that implicit operands match the instruction definition,
so they have to be $vcc even in wave32 mode. Use the mirFileLoaded hook
to fix them after MIParser's checks, converting them to $vcc_lo which is
what that rest of CodeGen expects.
This is all just extending the fixImplicitOperands hack which was
introduced with GFX10, but at least it makes it possible to write a MIR
test which creates the same instructions that normal CodeGen would
generate.
Commit: 9430a4b9d272b050869958d5f0e7ef9fd9db2643
https://github.com/llvm/llvm-project/commit/9430a4b9d272b050869958d5f0e7ef9fd9db2643
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Use getEdgeMask when constructing VPBlendRecipe (NFCI).
After 2d0d65b3babe, block-in and edge masks are create up-front. Only
retrieve the cached edge-mask here.
Commit: a4558a4a53eda8d170bbd2c358d383bb0a13f91f
https://github.com/llvm/llvm-project/commit/a4558a4a53eda8d170bbd2c358d383bb0a13f91f
Author: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/test/CodeGen/PowerPC/rldimi.ll
Log Message:
-----------
[PowerPC] Implement 32-bit expansion for rldimi (#86783)
rldimi is 64-bit instruction, due to backward compatibility, it needs to
be expanded into series of rotate and masking in 32-bit environment. In
the future, we may improve bit permutation selector and remove such
direct codegen.
Commit: db080605124db107e4f58cd285941a0c498675b1
https://github.com/llvm/llvm-project/commit/db080605124db107e4f58cd285941a0c498675b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Object/GOFFObjectFile.cpp
Log Message:
-----------
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.
Commit: 4ae33c52f794dbd64924dd006570cdc409c297bc
https://github.com/llvm/llvm-project/commit/4ae33c52f794dbd64924dd006570cdc409c297bc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
Log Message:
-----------
Fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFC.
Commit: 24e8c6a09b7d226dbe706aeae7aebf479a1e5087
https://github.com/llvm/llvm-project/commit/24e8c6a09b7d226dbe706aeae7aebf479a1e5087
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
Log Message:
-----------
[RISCV] Convert remaining constant splats in tests to use splat shorthand. NFC (#88099)
This follows on from #87616, but includes the tests with codegen
differences. These are presumably due to the fact that the splat is now
a constant expression. They don't seem to affect anything that we were
specifically testing for.
Commit: 45aec9a0b54e6d87abf75e960c96f59408edc706
https://github.com/llvm/llvm-project/commit/45aec9a0b54e6d87abf75e960c96f59408edc706
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Serialization/ASTReaderDecl.cpp
Log Message:
-----------
[NFC] [Serialization] Remove redundant hasPendingBody member
The hasPendingBody member is redundant with the
PendingBodies.count(Decl*) method. This patch removes the redundant
hasPendingBody member and the corresponding InterestingDecl struct.
Commit: 0bbe953aa3289a32cd816647820c8676bb3a61bc
https://github.com/llvm/llvm-project/commit/0bbe953aa3289a32cd816647820c8676bb3a61bc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-half-conversions.ll
Log Message:
-----------
[X86] Fold extract_subvector(cvtps2dq(x),c) -> cvtps2dq(extract_subvector(x,c))
Help unblock #83402
Commit: c83698367125703827f1b739393f006c399cb213
https://github.com/llvm/llvm-project/commit/c83698367125703827f1b739393f006c399cb213
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
M llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
A llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Remove unused first mask op from VPBlendRecipe. (#87770)
VPBlendRecipe does not use the first mask operand. Removing it allows
VPlan-based DCE to remove unused mask computations.
This also fixes #87410, where unused Not VPInstructions are considered
having only their first lane demanded, but some of their operands
providing a vector value due to other users.
Fixes https://github.com/llvm/llvm-project/issues/87410
PR: https://github.com/llvm/llvm-project/pull/87770
Commit: 321f8312b98620131ebb3b71fe15c0d6b2267488
https://github.com/llvm/llvm-project/commit/321f8312b98620131ebb3b71fe15c0d6b2267488
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
A clang/test/AST/Interp/weak.cpp
Log Message:
-----------
[clang][Interp] Diagnose comparisons with weak pointers
Commit: 5d7d6ad663f80fbc6161da1175476bb663301c46
https://github.com/llvm/llvm-project/commit/5d7d6ad663f80fbc6161da1175476bb663301c46
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/unittests/AST/Interp/CMakeLists.txt
A clang/unittests/AST/Interp/toAPValue.cpp
Log Message:
-----------
[clang][Interp] Add toAPValue unittests
Commit: 8795822f6ae2e82e23f7fd87a84d6d273e6c04ac
https://github.com/llvm/llvm-project/commit/8795822f6ae2e82e23f7fd87a84d6d273e6c04ac
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
Log Message:
-----------
[NFC][LLVM][CodeGen] Refactor SVE unpredicated binop isel patterns. (#84045)
Create PatFrags for fadd, fmul, fsub, mul, smulh and umulh so that a
single set of patterns can be used. Patch then removes unused classes
and some redundant whitespace.
Commit: 040e0d4fa45f3606fb584c2923dd111cca675feb
https://github.com/llvm/llvm-project/commit/040e0d4fa45f3606fb584c2923dd111cca675feb
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/Fortran-parsers.cpp
M flang/test/Parser/compiler-directives.f90
Log Message:
-----------
[flang]Accept directive inside type definition (#87804)
Some applications have alignment directives for members inside types.
This allows those to be present, but generally getting ignored [with a warning]
later on in the processing. This is just to allow the compilation to complete.
Commit: bf0b21aa685264c65a2d7fd4a8b86e3c42dfd729
https://github.com/llvm/llvm-project/commit/bf0b21aa685264c65a2d7fd4a8b86e3c42dfd729
Author: Hirofumi Nakamura <k.nakamura.hirofumi at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/unittests/Format/FormatTestTableGen.cpp
Log Message:
-----------
[clang-format] Remove trailing newlines in TableGen formatting test. (#87983)
Commit: 4023329bbfab5f2abc5c035aad05820724a484cf
https://github.com/llvm/llvm-project/commit/4023329bbfab5f2abc5c035aad05820724a484cf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
Log Message:
-----------
[X86] collectConcatOps - add ability to recurse through insert_subvector chains
Allows us to match insert_subvector(insert_subvector(undef, insert_subvector(insert_subvector(undef, x, 0), y, 1), 0), 0),
insert_subvector(insert_subvector(undef, z, 0), w, 1), 2)
Commit: 866a1bc814b4d4cb9aa3890eae56ffa05431741d
https://github.com/llvm/llvm-project/commit/866a1bc814b4d4cb9aa3890eae56ffa05431741d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
Log Message:
-----------
[X86] Add test coverage for #88030
Commit: 4657ab1c968e486e9f45329daa07340ebcf3bffd
https://github.com/llvm/llvm-project/commit/4657ab1c968e486e9f45329daa07340ebcf3bffd
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp
Log Message:
-----------
[Clang][Sema] Fix crash when 'this' is used in a dependent class scope function template specialization that instantiates to a static member function (#87541)
This patch fixes a crash that happens when '`this`' is referenced
(implicitly or explicitly) in a dependent class scope function template
specialization that instantiates to a static member function. For
example:
```
template<typename T>
struct A
{
template<typename U>
static void f();
template<>
void f<int>()
{
this; // causes crash during instantiation
}
};
template struct A<int>;
```
This happens because during instantiation of the function body,
`Sema::getCurrentThisType` will return a null `QualType` which we
rebuild the `CXXThisExpr` with. A similar problem exists for implicit
class member access expressions in such contexts (which shouldn't really
happen within templates anyways per [class.mfct.non.static]
p2, but changing that is non-trivial). This patch fixes the crash by building
`UnresolvedLookupExpr`s instead of `MemberExpr`s for these implicit
member accesses, which will then be correctly rebuilt as `MemberExpr`s
during instantiation.
Commit: 6528f103663af2f08474c16a1bb9ca0f1c2ad31d
https://github.com/llvm/llvm-project/commit/6528f103663af2f08474c16a1bb9ca0f1c2ad31d
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
A mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
Log Message:
-----------
[MLIR][OpenMP] Group clause operands into structures and use them to define simplified op builders (#86797)
This patch introduces a set of composable structures grouping the MLIR
operands associated to each OpenMP clause. This makes it easier to keep
the MLIR representation for the same clause consistent throughout all
operations that accept it.
The relevant clause operand structures are grouped into per-operation
structures using a mixin pattern and used to define new operation
constructors. These constructors can be used to avoid having to get the
order of a possibly large list of operands right.
Missing clauses are documented as TODOs, as well as operands which are
part of the relevant operation's operand structure but cannot be
attached to the associated operation yet, due to missing op arguments to
its MLIR definition.
A follow-up patch will update Flang lowering to make use of these
structures, simplifying the passing of information from clause
processing to operation-generating functions and also simplifying the
creation of operations through the use of the new operation
constructors.
Commit: a4cf479cdf08093b69177dd9adf32eebf3632dc3
https://github.com/llvm/llvm-project/commit/a4cf479cdf08093b69177dd9adf32eebf3632dc3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
Log Message:
-----------
[X86] shuffle-vs-trunc-128.ll - add BWVL-ONLY/VBMI/VBMI-FAST/VBMI-SLOW check prefixes to recover missing test checks
It is VERY annoying that update_llc_test_checks.py silently fails instead of correctly warning when this happens :(
Commit: 38824f285f1459cb890337d2df1a3cafd3fd109d
https://github.com/llvm/llvm-project/commit/38824f285f1459cb890337d2df1a3cafd3fd109d
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/CodeGenCXX/cxx2b-deducing-this.cpp
A clang/test/PCH/cxx23-deducing-this-lambda.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
Log Message:
-----------
[Clang] [Sema] Fix dependence of DREs in lambdas with an explicit object parameter (#84473)
This fixes some problems wrt dependence of captures in lambdas with
an explicit object parameter.
[temp.dep.expr] states that
> An id-expression is type-dependent if [...] its terminal name is
> - associated by name lookup with an entity captured by copy
> ([expr.prim.lambda.capture]) in a lambda-expression that has
> an explicit object parameter whose type is dependent [dcl.fct].
There were several issues with our implementation of this:
1. we were treating by-reference captures as dependent rather than
by-value captures;
2. tree transform wasn't checking whether referring to such a
by-value capture should make a DRE dependent;
3. when checking whether a DRE refers to such a by-value capture, we
were only looking at the immediately enclosing lambda, and not
at any parent lambdas;
4. we also forgot to check for implicit by-value captures;
5. lastly, we were attempting to determine whether a lambda has an
explicit object parameter by checking the `LambdaScopeInfo`'s
`ExplicitObjectParameter`, but it seems that that simply wasn't
set (yet) by the time we got to the check.
All of these should be fixed now.
This fixes #70604, #79754, #84163, #84425, #86054, #86398, and #86399.
Commit: 961d91abd375100a498807a5a0da8003a2878284
https://github.com/llvm/llvm-project/commit/961d91abd375100a498807a5a0da8003a2878284
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
Log Message:
-----------
[X86] shuffle-vs-trunc-128.ll - add common AVX2 check prefix
Commit: 6f6336858e4588ebd113ebcc930f6384a4edca54
https://github.com/llvm/llvm-project/commit/6f6336858e4588ebd113ebcc930f6384a4edca54
Author: Billy Zhu <billyzhu at modular.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/test/CAPI/llvm.c
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
[MLIR][LLVM] Add DebugNameTableKind to DICompileUnit (#87974)
Add the DebugNameTableKind field to DICompileUnit, along with its
importer & exporter.
Commit: 1e44d9ac5e9d1ff8baa99fd5495477f3f2f1abe6
https://github.com/llvm/llvm-project/commit/1e44d9ac5e9d1ff8baa99fd5495477f3f2f1abe6
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
Log Message:
-----------
[SPIR-V] Map llvm.{min,max}num to GL::N{Min,Max} (#88009)
SPIR-V intsruction selection was mapping the LLVM float min/max
intrinsics to FMin and FMax respectively for GL/Vulkan environments,
which does not match the intrinsics' documented treatment of NaN
operands. This patch switches the mapping to the correctly matched NMin
and NMax operations.
Fixes #87072
Commit: 0c92f8646a765174b68797ad3c0842215c77752f
https://github.com/llvm/llvm-project/commit/0c92f8646a765174b68797ad3c0842215c77752f
Author: Charalampos Mitrodimas <charmitro at posteo.net>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
A clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp
Log Message:
-----------
[clang] Disable missing definition warning on pure virtual functions (#74510)
Warning '-Wundefined-func-template' incorrectly indicates that no
definition is available for a pure virtual function. However, a
definition is not needed for a pure virtual function.
Fixes #74016
Commit: d022f6b8ff94bb13d12d39f23a3c3e7836e90756
https://github.com/llvm/llvm-project/commit/d022f6b8ff94bb13d12d39f23a3c3e7836e90756
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/test/Headers/Inputs/include/stdint.h
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[Libomp] Place generated OpenMP headers into build resource directory (#88007)
Summary:
These headers are a part of the compiler's resource directory once
installed. However, they are currently placed in the binary directory
temporarily. This makes it more difficult to use the compiler out of the
build directory and will cause issues when moving to `liboffload`. This
patch changes the logic to write these instead to the copmiler's
resource directory inside of the build tree.
NOTE: This doesn't change the Fortran headers, I don't know enough about
those and it won't use the same directory.
Commit: 2875e2448c147d8a2335882819acdd4c8eb97ea6
https://github.com/llvm/llvm-project/commit/2875e2448c147d8a2335882819acdd4c8eb97ea6
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/test/Lexer/cxx-features.cpp
M clang/www/cxx_status.html
Log Message:
-----------
Update __cpp_concepts macro (#87998)
After discussion with a few others, and seeing the state of our concepts
support, I believe it is worth trying to see if we can update this for
Clang19. The forcing function is that libstdc++'s `<expected>` header is
guarded by this macro, so we need to update it to support that.
Commit: 3f71d29e2370912ccc0384adce640c554561edd2
https://github.com/llvm/llvm-project/commit/3f71d29e2370912ccc0384adce640c554561edd2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/ms.cpp
Log Message:
-----------
[clang][Interp] Handle __unaligned in alignof expressions
Commit: 23b058cb7f2da7778eb66dbe44d5e60390264e4b
https://github.com/llvm/llvm-project/commit/23b058cb7f2da7778eb66dbe44d5e60390264e4b
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
A llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll
Log Message:
-----------
[SPIR-V] Re-implement switch and improve validation of forward calls (#87823)
This PR fixes issue https://github.com/llvm/llvm-project/issues/87763
and preserves valid CFG in cases when previous scheme failed to generate
valid code for a switch statement. The PR hardens one existing test case
and adds one more test case as a validation of a new switch generation.
Tests are passing spirv-val now.
This PR also improves validation of forward calls.
Commit: e47fd09f8eece712707f9611992cf6cfcd66605e
https://github.com/llvm/llvm-project/commit/e47fd09f8eece712707f9611992cf6cfcd66605e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
Log Message:
-----------
[RISCV] Use shNadd for scalable stack offsets (#88062)
If we need to multiply VLENB by 2, 4, or 8 and add it to the stack
pointer, we can do so with a shNadd instead of separate shift and add
instructions.
Commit: 5278594d7ef8c6814578f2f600016fef5ad058c9
https://github.com/llvm/llvm-project/commit/5278594d7ef8c6814578f2f600016fef5ad058c9
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Misc/warning-flags.c
A clang/test/Sema/tentative-array-decl.c
Log Message:
-----------
Add a diagnostic group for tentative array definitions
This diagnostic is one of the ones that GCC also does not have a
warning group for, but a user requested adding a group to control
selectively turning off this diagnostic. So this adds the diagnostic
to a new group, -Wtentative-definition-array
Fixes #87766
Commit: 3bfd5c64240c1a812c596dd2bcd480b7607155de
https://github.com/llvm/llvm-project/commit/3bfd5c64240c1a812c596dd2bcd480b7607155de
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
Log Message:
-----------
[TTI] getCommonMaskedMemoryOpCost - consistently use getScalarizationOverhead instead of ExtractElement costs for address/mask extraction. (#87771)
These aren't unknown extraction indices, we will be extracting every address/mask element in sequence.
Commit: c8917048e3aa2be03b6588b817730abdbce23c85
https://github.com/llvm/llvm-project/commit/c8917048e3aa2be03b6588b817730abdbce23c85
Author: Jakub Mazurkiewicz <mazkuba3 at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/Status/Cxx23.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/include/__functional/bind_back.h
M libcxx/include/functional
M libcxx/include/version
M libcxx/modules/std/functional.inc
M libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/types.h
M libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Implement `bind_back` (#81055)
Implement `std::bind_back` function from P2387R3 "Pipe support for
user-defined range adaptors".
Commit: fb8dbd1fb67ef4d1417f279df7f9a99b29468527
https://github.com/llvm/llvm-project/commit/fb8dbd1fb67ef4d1417f279df7f9a99b29468527
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.mir
M llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
Log Message:
-----------
[AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)
7dc20ab introduced an extra COPY when spilling and filling a PNR
register, which can't be elided as the input (PNR predicate) and output
(PPR predicate) register classes differ. The patch adds a new register
class that covers both PPR and PNR so that STR_PXI and LDR_PXI can
take either of them, removing the need for the copy.
Commit: 93f0880869419ffa3c7bb66b178f2453ea9d2bed
https://github.com/llvm/llvm-project/commit/93f0880869419ffa3c7bb66b178f2453ea9d2bed
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel][clang] Remove gen-clang-*-left-list attributes from tablegen
For both 9391ff8c86007562d40c240ea082b7c0cbf35947 and a30662fc2acdd73ca1a9217716299a4676999fb4.
Commit: 568ec1340c1260c36a490d10c38366ed00f63209
https://github.com/llvm/llvm-project/commit/568ec1340c1260c36a490d10c38366ed00f63209
Author: Kazu Hirata <kazu at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/RawMemProfReader.cpp
Log Message:
-----------
[memprof] Use structured binding (NFC) (#88096)
Commit: e280407a4865542c4bb6cfa148edbe1ea67023d6
https://github.com/llvm/llvm-project/commit/e280407a4865542c4bb6cfa148edbe1ea67023d6
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__expected/bad_expected_access.h
A libcxx/test/std/utilities/expected/expected.bad/base.compile.pass.cpp
A libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp
R libcxx/test/std/utilities/expected/expected.bad/what.noexcept.compile.pass.cpp
A libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp
Log Message:
-----------
[libc++] Add test coverage for our implementation of LWG4031 (#87508)
This was actually already implemented in the initial version of
std::expected, but this patch adds test coverage and makes it more
explicit that we intend to make these functions noexcept.
Commit: 4ac2721e51131b3a160fee5ae0fcbd695d090e86
https://github.com/llvm/llvm-project/commit/4ac2721e51131b3a160fee5ae0fcbd695d090e86
Author: David Green <david.green at arm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll
Log Message:
-----------
[AArch64] Add costs for ST3 and ST4 instructions, modelled as store(shuffle). (#87934)
This tries to add some costs for the shuffle in a ST3/ST4 instruction,
which are represented in LLVM IR as store(interleaving shuffle). In
order to detect the store, it needs to add a CxtI context instruction to
check the users of the shuffle. LD3 and LD4 are added, LD2 should be a
zip1 shuffle, which will be added in another patch.
It should help fix some of the regressions from #87510.
Commit: e8e67957fa48fd7611adccef1a0449b83649c9f4
https://github.com/llvm/llvm-project/commit/e8e67957fa48fd7611adccef1a0449b83649c9f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll
Log Message:
-----------
[SLP]Fix PR88123: use vectorized operands consistently.
Need to use vectorized operands, not the vecop of the extractelement
instructions, to avoid false detection of the extra vector operand in
the extractelements shuffling.
Commit: 8a8ab8f70cbb5507d1aa55efcd9c6e61ad4e891c
https://github.com/llvm/llvm-project/commit/8a8ab8f70cbb5507d1aa55efcd9c6e61ad4e891c
Author: Schuyler Eldridge <schuyler.eldridge at sifive.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M .github/workflows/release-lit.yml
Log Message:
-----------
[lit][ci] Publish lit wheels (#88072)
Add wheel publishing in addition to existing source distribution
publishing of lit.
Fixes #63369. This also uses the exact fix proposed by @EFord36 in
#63369.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge at sifive.com>
Commit: 4bb5d48584818646a31a1ba4bfbbd658b7dfbe67
https://github.com/llvm/llvm-project/commit/4bb5d48584818646a31a1ba4bfbbd658b7dfbe67
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/test/Driver/cuda-external-tools.cu
Log Message:
-----------
[clang][NFC] Fix CUDA clang-cl tests
- Add '--' argument to prevent interpreting intput files as options
starting with '/'. Fix test failure after
2921a0928c71f4ee652a2478283e47ab5ffebf58.
Commit: 614a5780347ff0c8f82b8867660ea7fb4d9fdccb
https://github.com/llvm/llvm-project/commit/614a5780347ff0c8f82b8867660ea7fb4d9fdccb
Author: Peter Lafreniere <peter at n8pjl.ca>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
A llvm/test/CodeGen/M68k/Arith/unary.ll
M llvm/test/CodeGen/M68k/Atomics/rmw.ll
M llvm/test/MC/Disassembler/M68k/arithmetic.txt
A llvm/test/MC/M68k/Arith/Classes/MxNOT.s
Log Message:
-----------
[M68k] Add support for bitwise NOT instruction (#88049)
Currently the bitwise NOT instruction is not recognized. Add support for
using NOT on data registers. This is a partial implementation that puts
NOT at the same level of support as NEG currently enjoys.
Using not rather than eori cuts the length of the encoded instruction
in half or in thirds, leading to a reduction of 4-10 cycles per
instruction, on the original 68000.
This change includes tests for both bitwise and arithmetic negation.
Commit: 71ffc1f0ea1c64d475d9248ea7c68dfec16ee1ab
https://github.com/llvm/llvm-project/commit/71ffc1f0ea1c64d475d9248ea7c68dfec16ee1ab
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/FmaTest.h
Log Message:
-----------
[libc] Initialize rand for fma tests (#88055)
Summary:
The GPU build will have some random garbage here since we do not support
initializers for the underlying implementation. Manually set the seed to
1.
Commit: f0e79d9152b04845e60fc97ca6a4e7760202afbb
https://github.com/llvm/llvm-project/commit/f0e79d9152b04845e60fc97ca6a4e7760202afbb
Author: David Green <david.green at arm.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
Log Message:
-----------
[AArch64] Add a cost for identity shuffles.
These are mostly handled at a higher level when costing shuffles, but some
masks can end up being identity or concat masks which we can treat as free.
Commit: 3009228a09dbfe04e0911fc19813ec72d389bc45
https://github.com/llvm/llvm-project/commit/3009228a09dbfe04e0911fc19813ec72d389bc45
Author: Michael Halkenhäuser <MichaelGerald.Halkenhauser at amd.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M clang/test/CodeGen/ubsan-bitfield-conversion.c
M clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp
Log Message:
-----------
[clang][UBSan] Remove rigid metadata checks for `ubsan-bitfield-conversion` (#88116)
Follow-up to discussion: https://github.com/llvm/llvm-project/pull/87761
As discussed after landing the original PR:
Since fails could happen w.r.t. checking `!6`, these checks should be
removed.
Commit: 95027ca56a9d466d80fa00166573eba4fc911c5f
https://github.com/llvm/llvm-project/commit/95027ca56a9d466d80fa00166573eba4fc911c5f
Author: Alex Richardson <alexrichardson at google.com>
Date: 2024-04-09 (Tue, 09 Apr 2024)
Changed paths:
M .github/workflows/release-lit.yml
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Disasm.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/AST/Interp/Pointer.cpp
M clang/lib/AST/Interp/Record.cpp
M clang/lib/AST/Interp/Record.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/APINotes/retain-count-convention.m
M clang/test/APINotes/versioned.m
M clang/test/AST/Interp/arrays.cpp
M clang/test/AST/Interp/ms.cpp
A clang/test/AST/Interp/weak.cpp
M clang/test/AST/ast-print-method-decl.cpp
M clang/test/AST/ast-print-no-sanitize.cpp
M clang/test/AST/attr-print-emit.cpp
M clang/test/Analysis/scopes-cfg-output.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c
M clang/test/CodeGen/ubsan-bitfield-conversion.c
M clang/test/CodeGenCXX/cxx2b-deducing-this.cpp
M clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp
M clang/test/Driver/arm-compiler-rt.c
M clang/test/Driver/cl-link.c
M clang/test/Driver/compiler-rt-unwind.c
M clang/test/Driver/coverage-ld.c
M clang/test/Driver/cuda-external-tools.cu
M clang/test/Driver/instrprof-ld.c
M clang/test/Driver/linux-ld.c
M clang/test/Driver/mingw-sanitizers.c
M clang/test/Driver/msp430-toolchain.c
M clang/test/Driver/print-libgcc-file-name-clangrt.c
M clang/test/Driver/print-runtime-dir.c
M clang/test/Driver/riscv32-toolchain-extra.c
M clang/test/Driver/riscv32-toolchain.c
M clang/test/Driver/riscv64-toolchain-extra.c
M clang/test/Driver/riscv64-toolchain.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Driver/wasm-toolchain.c
M clang/test/Driver/wasm-toolchain.cpp
M clang/test/Driver/windows-cross.c
M clang/test/Driver/zos-ld.c
M clang/test/Lexer/cxx-features.cpp
M clang/test/Misc/warning-flags.c
M clang/test/OpenMP/assumes_codegen.cpp
M clang/test/OpenMP/assumes_print.cpp
M clang/test/OpenMP/assumes_template_print.cpp
M clang/test/OpenMP/declare_simd_ast_print.cpp
A clang/test/PCH/cxx23-deducing-this-lambda.cpp
A clang/test/Sema/tentative-array-decl.c
M clang/test/SemaCXX/attr-no-sanitize.cpp
M clang/test/SemaCXX/cxx11-attr-print.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
A clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp
M clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp
M clang/unittests/AST/Interp/CMakeLists.txt
A clang/unittests/AST/Interp/toAPValue.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestTableGen.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M clang/www/cxx_status.html
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/memprof/tests/CMakeLists.txt
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/test/Driver/msvc-dependent-lib-flags.f90
M flang/test/Parser/compiler-directives.f90
M libc/include/llvm-libc-macros/math-macros.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/FmaTest.h
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/Status/Cxx23.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__expected/bad_expected_access.h
M libcxx/include/__functional/bind_back.h
M libcxx/include/functional
M libcxx/include/version
M libcxx/modules/std/functional.inc
M libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/std/utilities/expected/expected.bad/base.compile.pass.cpp
A libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp
R libcxx/test/std/utilities/expected/expected.bad/what.noexcept.compile.pass.cpp
A libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp
A libcxx/test/std/utilities/function.objects/func.bind.partial/types.h
M libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i
M lldb/bindings/interface/SBProcessDocstrings.i
M lldb/bindings/interface/SBQueueDocstrings.i
M lldb/bindings/interface/SBThreadDocstrings.i
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/Support/ToolOutputFile.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/RawMemProfReader.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Support/ToolOutputFile.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
A llvm/test/CodeGen/M68k/Arith/unary.ll
M llvm/test/CodeGen/M68k/Atomics/rmw.ll
M llvm/test/CodeGen/PowerPC/ppcsoftops.ll
M llvm/test/CodeGen/PowerPC/rldimi.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
M llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
A llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll
M llvm/test/CodeGen/X86/patchable-prologue.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll
M llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
M llvm/test/MC/Disassembler/M68k/arithmetic.txt
A llvm/test/MC/M68k/Arith/Classes/MxNOT.s
M llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll
M llvm/test/Transforms/InstCombine/insertelement.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
M llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
M llvm/test/Transforms/LoopVectorize/if-reduction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
A llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
A llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll
M llvm/test/Transforms/lower-builtin-allow-check.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td
A mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/IR/AffineExprVisitor.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/test/CAPI/llvm.c
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
M mlir/test/IR/affine-walk.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M openmp/runtime/src/CMakeLists.txt
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
fix typo in comment
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/92133bb2f6d8...95027ca56a9d
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list