[all-commits] [llvm/llvm-project] fb8dbd: [AArch64] Remove copy in SVE/SME predicate spill a...

[Sam Tebbs via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fb8dbd1fb67ef4d1417f279df7f9a99b29468527
      https://github.com/llvm/llvm-project/commit/fb8dbd1fb67ef4d1417f279df7f9a99b29468527
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir
    M llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s

  Log Message:
  -----------
  [AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)

7dc20ab introduced an extra COPY when spilling and filling a PNR
register, which can't be elided as the input (PNR predicate) and output
(PPR predicate) register classes differ. The patch adds a new register
class that covers both PPR and PNR so that STR_PXI and LDR_PXI can
take either of them, removing the need for the copy.



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