[all-commits] [llvm/llvm-project] 9c6603: [RISCV] Support vwsll in combineBinOp_VLToVWBinOp_...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9c660362c4fb05c0198b9d3ed65b2344706129bd
      https://github.com/llvm/llvm-project/commit/9c660362c4fb05c0198b9d3ed65b2344706129bd
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

  Log Message:
  -----------
  [RISCV] Support vwsll in combineBinOp_VLToVWBinOp_VL (#87620)

If the subtarget has +zvbb then we can attempt folding shl and shl_vl to
vwsll nodes.

There are few test cases where we still don't pick up the vwsll:
- For fixed vector vwsll.vi on RV32, see the FIXME for VMV_V_X_VL in
fillUpExtensionSupport for support implicit sign extension
- For scalable vector vwsll.vi we need to support ISD::SPLAT_VECTOR, see
#87249



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