[all-commits] [llvm/llvm-project] ac321c: [AArch64][GlobalISel] Legalize Insert vector eleme...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac321cbb0350996ceef4e6d9e8a1035880609288
      https://github.com/llvm/llvm-project/commit/ac321cbb0350996ceef4e6d9e8a1035880609288
  Author: David Green <david.green at arm.com>
  Date:   2024-04-08 (Mon, 08 Apr 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Legalize Insert vector element (#81453)

This attempts to standardize and extend some of the insert vector
element lowering. Most notably:
- More types are handled by splitting illegal vectors.
- The index type for G_INSERT_VECTOR_ELT is canonicalized to
  TLI.getVectorIdxTy(), similar to extact_vector_element.
- Some of the existing patterns now have the index type specified to
  make sure they can apply to GISel too.
- The C++ selection code has been removed, relying on tablegen patterns.
- G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to
  use a i32 type, allowing the existing patterns to apply.
- Variable index inserts are lowered in post-legalizer lowering,
  expanding into a stack store and reload.



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