[all-commits] [llvm/llvm-project] d38bff: [AArch64] SimplifyDemandedBitsForTargetNode - add ...

[Sizov Nikita via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d38bff460acb4fe3156d90ec739da49344db14ca
      https://github.com/llvm/llvm-project/commit/d38bff460acb4fe3156d90ec739da49344db14ca
  Author: Sizov Nikita <s.nikita.v at gmail.com>
  Date:   2024-04-06 (Sat, 06 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll

  Log Message:
  -----------
  [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (#76644)

Fold BICi if all destination bits are already known to be zeroes

```llvm
define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) {
  %x0 = zext <8 x i8> %a0 to <8 x i16>
  %x1 = zext <8 x i8> %a1 to <8 x i16>
  %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
  %res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
  ret <8 x i16> %res
}
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
```

```
haddu_known:                            // @haddu_known
        ushll   v0.8h, v0.8b, #0
        ushll   v1.8h, v1.8b, #0
        uhadd   v0.8h, v0.8h, v1.8h
        bic     v0.8h, #254, lsl #8 <-- this one will be removed as we know high bits are zero extended
        ret
```

Fixes #53881
Fixes #53622



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