[all-commits] [llvm/llvm-project] 10bd55: [RISCV] Model vd as a src for some Zvk* instructio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 10bd55566a01c63d9e4f46da5a4e671684aa7fc5
      https://github.com/llvm/llvm-project/commit/10bd55566a01c63d9e4f46da5a4e671684aa7fc5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-27 (Wed, 27 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

  Log Message:
  -----------
  [RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710)

Some Zvk instructions use vd as a source regardless of tail policy.
Model this in the MC layer. We already do this for FMA for example.



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