[all-commits] [llvm/llvm-project] baf66e: [Target][RISCV] Add HwMode support to subregister ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb
      https://github.com/llvm/llvm-project/commit/baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-27 (Wed, 27 Mar 2024)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/TableGen/ConcatenatedSubregs.td
    A llvm/test/TableGen/HwModeSubRegs.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/Common/InfoByHwMode.cpp
    M llvm/utils/TableGen/Common/InfoByHwMode.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)

This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already uses HwMode. Previously we
said the subreg indices have unknown size and offset, but this stops
DwarfExpression::addMachineReg from being able to find the registers
that make up the pair.

I believe this fixes https://github.com/llvm/llvm-project/issues/85864
but need to verify.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications