[all-commits] [llvm/llvm-project] 6c1d44: [SLP]Improve minbitwidth analysis for shifts.

[Alexey Bataev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c1d4454ad00414cf20f9a69e04856de99f6bf1d
      https://github.com/llvm/llvm-project/commit/6c1d4454ad00414cf20f9a69e04856de99f6bf1d
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-03-20 (Wed, 20 Mar 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll

  Log Message:
  -----------
  [SLP]Improve minbitwidth analysis for shifts.

Adds improved bitwidth analysis for shl/ashr/lshr instructions. The
analysis is based on similar version in InstCombiner.

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/84356



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