[all-commits] [llvm/llvm-project] 81d9ed: [SLP]Do extra analysis int minbitwidth if some che...

[Alexey Bataev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81d9ed605b126d163f2f1cc226c639f1dfdc5224
      https://github.com/llvm/llvm-project/commit/81d9ed605b126d163f2f1cc226c639f1dfdc5224
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-03-20 (Wed, 20 Mar 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
    A llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-but-not-operands.ll

  Log Message:
  -----------
  [SLP]Do extra analysis int minbitwidth if some checks return false.

The instruction itself can be considered good for minbitwidth casting,
even if one of the operand checks returns false.

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/84363



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