[all-commits] [llvm/llvm-project] 0858c9: [X86] Add missing register qualifier to the VBLEND...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0858c906db008e02163e159158c082d9fc82dcca
      https://github.com/llvm/llvm-project/commit/0858c906db008e02163e159158c082d9fc82dcca
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-03-11 (Mon, 11 Mar 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86FastISel.cpp
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/lib/Target/X86/X86SchedAlderlakeP.td
    M llvm/lib/Target/X86/X86SchedSapphireRapids.td
    M llvm/test/TableGen/x86-fold-tables.inc

  Log Message:
  -----------
  [X86] Add missing register qualifier to the VBLENDVPD/VBLENDVPS/VPBLENDVB instruction names

Matches the SSE variants (which has a 0 qualifier to indicate the xmm0 explicit dependency)


  Commit: ad8c8281363261929b53b0a519cd20e9e2445343
      https://github.com/llvm/llvm-project/commit/ad8c8281363261929b53b0a519cd20e9e2445343
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-03-11 (Mon, 11 Mar 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse41.s

  Log Message:
  -----------
  [X86] (V)MPSADBW instructions can run on Port1 or Port5 for one uop stage

When we copied the IceLake model from the SkylakeServer model we missed this diff

Confirmed with uops.info and Agner


Compare: https://github.com/llvm/llvm-project/compare/a924da6d4b87...ad8c82813632

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