[all-commits] [llvm/llvm-project] a924da: [mlir][IR] Add `isInteger()` (without width) (#84467)

[Marius Brehler via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a924da6d4b8733e5bf08098b18dd7ad1a5ba5f46
      https://github.com/llvm/llvm-project/commit/a924da6d4b8733e5bf08098b18dd7ad1a5ba5f46
  Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
  Date:   2024-03-11 (Mon, 11 Mar 2024)

  Changed paths:
    M mlir/include/mlir/IR/Types.h
    M mlir/lib/IR/Types.cpp

  Log Message:
  -----------
  [mlir][IR] Add `isInteger()` (without width) (#84467)

For the singless and signed integers overloads exist, so that the width
does not need to be specified as an argument. This adds the same for
integers without checking for signedness.



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