[all-commits] [llvm/llvm-project] c16172: [RISCV] Slightly improve expanded multiply emulati...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c161720ab49ed426e50f70c09da9b0c04be0f50f
      https://github.com/llvm/llvm-project/commit/c161720ab49ed426e50f70c09da9b0c04be0f50f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-03-06 (Wed, 06 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll

  Log Message:
  -----------
  [RISCV] Slightly improve expanded multiply emulation in getVLENFactoredAmount. (#84113)

Instead of initializing the accumulator to 0. Initialize it on first
assignment with a mv from the register that holds VLENB << ShiftAmount.

Fix a missing kill flag on the final Add.

I have no real interest in this case, just an easy optimization I
noticed.



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