[all-commits] [llvm/llvm-project] 6f5c4f: [mlir][vector]Add Vector bitwidth target to Linear...

[Balaji V. Iyer. via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f5c4f2eacf24cecfc0faf0a204137ce65eecc2d
      https://github.com/llvm/llvm-project/commit/6f5c4f2eacf24cecfc0faf0a204137ce65eecc2d
  Author: Balaji V. Iyer <43187390+bviyer at users.noreply.github.com>
  Date:   2024-03-04 (Mon, 04 Mar 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
    M mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
    M mlir/test/Dialect/Vector/linearize.mlir
    M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp

  Log Message:
  -----------
  [mlir][vector]Add Vector bitwidth target to Linearize Vectorizable and Constant Ops (#83314)

Added a new flag `targetVectorBitwidth` to capture bit-width input.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications