[all-commits] [llvm/llvm-project] a5c90e: [LoongArch] Switch to the Machine Scheduler (#83759)

[wanglei via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a5c90e48b6f11bc6db7344503589648f76b16d80
      https://github.com/llvm/llvm-project/commit/a5c90e48b6f11bc6db7344503589648f76b16d80
  Author: wanglei <wanglei at loongson.cn>
  Date:   2024-03-05 (Tue, 05 Mar 2024)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchSubtarget.h
    M llvm/test/CodeGen/LoongArch/alloca.ll
    M llvm/test/CodeGen/LoongArch/alsl.ll
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/bitreverse.ll
    M llvm/test/CodeGen/LoongArch/branch-relaxation.ll
    M llvm/test/CodeGen/LoongArch/bswap-bitreverse.ll
    M llvm/test/CodeGen/LoongArch/bswap.ll
    M llvm/test/CodeGen/LoongArch/bytepick.ll
    M llvm/test/CodeGen/LoongArch/calling-conv-common.ll
    M llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
    M llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll
    M llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
    M llvm/test/CodeGen/LoongArch/cfr-pseudo-copy.mir
    M llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/LoongArch/fcopysign.ll
    M llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
    M llvm/test/CodeGen/LoongArch/ghc-cc.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll
    M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
    M llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
    M llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
    M llvm/test/CodeGen/LoongArch/lasx/mulh.ll
    M llvm/test/CodeGen/LoongArch/lasx/vselect.ll
    M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
    M llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
    M llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
    M llvm/test/CodeGen/LoongArch/lsx/mulh.ll
    M llvm/test/CodeGen/LoongArch/lsx/vselect.ll
    M llvm/test/CodeGen/LoongArch/preferred-alignments.ll
    M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
    M llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
    M llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll
    M llvm/test/CodeGen/LoongArch/shrinkwrap.ll
    M llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
    M llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll
    M llvm/test/CodeGen/LoongArch/spill-ra-without-kill.ll
    M llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll
    M llvm/test/CodeGen/LoongArch/tail-calls.ll
    M llvm/test/CodeGen/LoongArch/unaligned-access.ll
    M llvm/test/CodeGen/LoongArch/vararg.ll
    M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
    M llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected

  Log Message:
  -----------
  [LoongArch] Switch to the Machine Scheduler (#83759)

The SelectionDAG scheduling preference now becomes source order
scheduling (machine scheduler generates better code -- even without
there being a machine model defined for LoongArch yet).

Most of the test changes are trivial instruction reorderings and
differing register allocations, without any obvious performance impact.

This is similar to commit: 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec



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