[all-commits] [llvm/llvm-project] ecc3bd: [SPIR-V] Fix bitcast legalization/instruction sele...

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecc3bdaae14a02acc879c018e21d58a83329dc6e
      https://github.com/llvm/llvm-project/commit/ecc3bdaae14a02acc879c018e21d58a83329dc6e
  Author: Vyacheslav Levytskyy <89994100+VyacheslavLevytskyy at users.noreply.github.com>
  Date:   2024-03-04 (Mon, 04 Mar 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
    A llvm/test/CodeGen/SPIRV/bitcast.ll

  Log Message:
  -----------
  [SPIR-V] Fix bitcast legalization/instruction selection in SPIR-V Backend (#83139)

This PR is to fix a way how SPIR-V Backend describes legality of
OpBitcast instruction and how it is validated on a step of instruction
selection. Instead of checking a size of virtual registers (that makes
no sense due to lack of guarantee of direct relations between size of
virtual register and bit width associated with the type size), this PR
allows to legalize OpBitcast without size check and postpones validation
to the instruction selection step.

As an example, let's consider the next example that was copied as is
from a bigger test suite:

```
  %355:id(s16) = G_BITCAST %301:id(s32)
  %303:id(s16) = ASSIGN_TYPE %355:id(s16), %349:type(s32)
  %644:fid(s32) = G_FMUL %645:fid, %646:fid
  %301:id(s32) = ASSIGN_TYPE %644:fid(s32), %40:type(s32)
```

Without the PR this leads to a crash with complains to an illegal
bitcast, because %355 is s16 and %301 is s32. However, we must check not
virtual registers in this case, but types of %355 and %301, i.e.,
%349:type(s32) and %40:type(s32), which are perfectly well compatible in
a sense of OpBitcast in this case.

In a test case that is a part of this PR OpBitcast is legal, being
applied for `OpTypeInt 16` and `OpTypeFloat 16`, but would not be
legalized without this PR due to virtual registers defined as having
size 16 and 32.



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