[all-commits] [llvm/llvm-project] 540d25: [SPIRV] Add vector reduction instructions (#82786)

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 540d255167742b6464a01f052d31c704fc4dd5aa
      https://github.com/llvm/llvm-project/commit/540d255167742b6464a01f052d31c704fc4dd5aa
  Author: Vyacheslav Levytskyy <89994100+VyacheslavLevytskyy at users.noreply.github.com>
  Date:   2024-03-04 (Mon, 04 Mar 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/CMakeLists.txt
    M llvm/lib/Target/SPIRV/SPIRV.h
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
    A llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll

  Log Message:
  -----------
  [SPIRV] Add vector reduction instructions (#82786)

This PR is to add vector reduction instructions according to
https://llvm.org/docs/GlobalISel/GenericOpcode.html#vector-reduction-operations
and widen in such a way a range of successful supported conversions,
covering new cases of vector reduction instructions which IRTranslator
is unable to resolve.

By legalizing vector reduction instructions we introduce a new
instruction patterns that should be addressed, including patterns that
are delegated to pre-legalize step. To address this problem, a new pass
is added that is to bring newly generated instructions after
legalization to an aspect required by instruction selection.

Expected overheads for existing cases is minimal, because a new pass is
working only with newly introduced instructions, otherwise it's just a
additional code traverse without any actions.



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