[all-commits] [llvm/llvm-project] 775bd6: [RISCV] Add scheduling info for Zcmp (#82719)

[Visoiu Mistrih Francis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 775bd60363353b78657967c80f0f109cdb65cf8f
      https://github.com/llvm/llvm-project/commit/775bd60363353b78657967c80f0f109cdb65cf8f
  Author: Visoiu Mistrih Francis <890283+francisvm at users.noreply.github.com>
  Date:   2024-02-23 (Fri, 23 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
    A llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir

  Log Message:
  -----------
  [RISCV] Add scheduling info for Zcmp (#82719)

The order of the entries in the list is:

outs, ins, Defs, Uses, implicit-defs, implicit uses, where the last two
are added programatically during codegen depending on the registers
saved/restored and are not described in the TD files.



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