[all-commits] [llvm/llvm-project] ae91a4: [X86][MC] Reject out-of-range control and debug re...

[Timothy Herchen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ae91a427ac8f9fc7368ec052995cec6a6aeb8ea8
      https://github.com/llvm/llvm-project/commit/ae91a427ac8f9fc7368ec052995cec6a6aeb8ea8
  Author: Timothy Herchen <timothy.herchen at gmail.com>
  Date:   2024-02-23 (Fri, 23 Feb 2024)

  Changed paths:
    M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
    M llvm/test/MC/Disassembler/X86/x86-64-err.txt

  Log Message:
  -----------
  [X86][MC] Reject out-of-range control and debug registers encoded with APX (#82584)

Fixes #82557. APX specification states that the high bits found in REX2
used to encode GPRs can also be used to encode control and debug
registers, although all of them will #UD. Therefore, when disassembling
we reject attempts to create control or debug registers with a value of
16 or more.

See page 22 of the
[specification](https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html):

> Note that the R, X and B register identifiers can also address non-GPR
register types, such as vector registers, control registers and debug
registers. When any of them does, the highest-order bits REX2.R4,
REX2.X4 or REX2.B4 are generally ignored, except when the register being
addressed is a control or debug register. [...] The exception is that
REX2.R4 and REX2.R3 [*sic*] are not ignored when the R register
identifier addresses a control or debug register. Furthermore, if any
attempt is made to access a non-existent control register (CR*) or debug
register (DR*) using the REX2 prefix and one of the following
instructions:
“MOV CR*, r64”, “MOV r64, CR*”, “MOV DR*, r64”, “MOV r64, DR*”. #UD is
raised.

The invalid encodings are 64-bit only because `0xd5` is a valid
instruction in 32-bit mode.



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