[all-commits] [llvm/llvm-project] aaf2d0: [Hexagon] Clean up redundant transfer instructions...

[Sumanth Gundapaneni via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aaf2d078b62251b867f37eaa94621dbbbfa0e5b0
      https://github.com/llvm/llvm-project/commit/aaf2d078b62251b867f37eaa94621dbbbfa0e5b0
  Author: Sumanth Gundapaneni <sgundapa at quicinc.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M llvm/lib/Target/Hexagon/CMakeLists.txt
    M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
    A llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
    M llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/Hexagon/isel/select-vec.ll
    M llvm/test/CodeGen/Hexagon/reg-by-name.ll
    A llvm/test/CodeGen/Hexagon/tfr-slotindex.ll

  Log Message:
  -----------
  [Hexagon] Clean up redundant transfer instructions. (#82663)

This patch adds a Hexagon specific backend pass that cleans up redundant
transfers after register allocation.



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