[all-commits] [llvm/llvm-project] 5b53fa: [RISCV] Enable -riscv-enable-sink-fold by default....

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b53fa04db33a931b843b32946065490513484bf
      https://github.com/llvm/llvm-project/commit/5b53fa04db33a931b843b32946065490513484bf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

  Log Message:
  -----------
  [RISCV] Enable -riscv-enable-sink-fold by default. (#82026)

AArch64 has had it enabled since late November, so hopefully the main
issues have been resolved.

I see a small reduction in dynamic instruction count on every benchmark
in specint2017. The best improvement was 0.3% so nothing amazing.



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