[all-commits] [llvm/llvm-project] 9eb5f9: [RISCV][AArch64] Add vscale_range attribute to tes...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9eb5f94f9b47154cf07160a6ba74ab1c31becfa3
      https://github.com/llvm/llvm-project/commit/9eb5f94f9b47154cf07160a6ba74ab1c31becfa3
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll

  Log Message:
  -----------
  [RISCV][AArch64] Add vscale_range attribute to tests per architecture minimums

Spent a bunch of time tracing down an odd issue "in SCEV" which turned out
to be the fact that SCEV doesn't have access to TTI.  As a result, the only
way for it to get range facts on vscales (to avoid collapsing ranges of
element counts and type sizes to trivial ranges on multiplies) is to look
at the vscale_range attribute.  Since vscale_range is set by clang by
default, manually setting it in the tests shouldn't interfere with the
test intent.



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