[all-commits] [llvm/llvm-project] 815644: [RISCV] Fix mgather -> riscv.masked.strided.load c...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 815644b4dd882ade2e5649d4f97c3dd6f7aea200
      https://github.com/llvm/llvm-project/commit/815644b4dd882ade2e5649d4f97c3dd6f7aea200
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-02-22 (Thu, 22 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  -----------
  [RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (#82506)

This fixes the miscompile reported in #82430 by telling
isSimpleVIDSequence to sign extend to XLen instead of the width of the
indices, since the "sequence" of indices generated by a strided load
will be at XLen.

This was the simplest way I could think of getting isSimpleVIDSequence
to treat the indexes as if they were zero extended to XLenVT.

Another way we could do this is by refactoring out the "get constant
integers" part from isSimpleVIDSequence and handle them as APInts so we
can separately zero extend it.

Fixes #82430



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