[all-commits] [llvm/llvm-project] 7fa858: [NFC][clang] Remove trailing whitespaces

[Florian Hahn via All-commits]

  Branch: refs/heads/users/fhahn/vplan-uniform-scalar-lanes
  Home:   https://github.com/llvm/llvm-project
  Commit: 7fa8585fdefd98dd73940c74165aa55da1175f02
      https://github.com/llvm/llvm-project/commit/7fa8585fdefd98dd73940c74165aa55da1175f02
  Author: Bill Wendling <morbo at google.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M clang/lib/InstallAPI/FileList.cpp

  Log Message:
  -----------
  [NFC][clang] Remove trailing whitespaces


  Commit: cb1fed3a89e0cdc2660edaada1f0868cae3b7bcf
      https://github.com/llvm/llvm-project/commit/cb1fed3a89e0cdc2660edaada1f0868cae3b7bcf
  Author: David Majnemer <david.majnemer at gmail.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

  Log Message:
  -----------
  [NVPTX] Correctly guard int -> bf16 on PTX version and SM version


  Commit: d4fd20258f63d30be638b04f10eaa469707759f0
      https://github.com/llvm/llvm-project/commit/d4fd20258f63d30be638b04f10eaa469707759f0
  Author: mlevesquedion <mlevesquedion at google.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
    M mlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
    M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
    M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
    M mlir/lib/Dialect/SCF/Utils/Utils.cpp
    M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
    M mlir/test/Conversion/AffineToStandard/lower-affine.mlir
    M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
    M mlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
    M mlir/test/Transforms/parametric-tiling.mlir

  Log Message:
  -----------
  [mlir] Use arith max or min ops instead of cmp + select (#82178)

I believe the semantics should be the same, but this saves 1 op and simplifies the code.

For example, the following two instructions:

```
%2 = cmp sgt %0, %1
%3 = select %2, %0, %1
```

Are equivalent to:

```
%2 = maxsi %0 %1
```


  Commit: fa8f74716010be635cbbd98146a0e58c9dd3c149
      https://github.com/llvm/llvm-project/commit/fa8f74716010be635cbbd98146a0e58c9dd3c149
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

  Log Message:
  -----------
  !fixup also use new scheme for in-loop reductions.


  Commit: cd160a6e98533fbc04a76d1b969db77b49668eb3
      https://github.com/llvm/llvm-project/commit/cd160a6e98533fbc04a76d1b969db77b49668eb3
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

  Log Message:
  -----------
  [VPlan] Do not add call results with void type to State (NFC).

With vector libraries, we may vectorize calls with void return types. Do
not add those values to the state; they can never be accessed.


  Commit: 57b42297a528d021293b87adf7fd635f1f99d9c0
      https://github.com/llvm/llvm-project/commit/57b42297a528d021293b87adf7fd635f1f99d9c0
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M clang/lib/InstallAPI/FileList.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
    M mlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
    M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
    M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
    M mlir/lib/Dialect/SCF/Utils/Utils.cpp
    M mlir/lib/Dialect/Tosa/Utils/ConversionUtils.cpp
    M mlir/test/Conversion/AffineToStandard/lower-affine.mlir
    M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
    M mlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir
    M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
    M mlir/test/Transforms/parametric-tiling.mlir

  Log Message:
  -----------
  Merge remote-tracking branch 'origin/main' into users/fhahn/vplan-uniform-scalar-lanes


Compare: https://github.com/llvm/llvm-project/compare/d72a629b3db4...57b42297a528

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