[all-commits] [llvm/llvm-project] f1e60c: [CodeGen] Convert RISCV Init Undef pass to support...

[Jack Styles via All-commits]

  Branch: refs/heads/users/stylie777/add_arm_init_undef_pass
  Home:   https://github.com/llvm/llvm-project
  Commit: f1e60cf0d39630e338f09355d363a6d3be5a25db
      https://github.com/llvm/llvm-project/commit/f1e60cf0d39630e338f09355d363a6d3be5a25db
  Author: Jack Styles <jack.styles at arm.com>
  Date:   2024-02-14 (Wed, 14 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/InitUndef.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    R llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
    M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
    M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

  Log Message:
  -----------
  [CodeGen] Convert RISCV Init Undef pass to support any architecture

Currently this pass is designed for RISC-V only, however this is
not the only architecture with the bug reported in issue #50157.
We can convert the exisiting pass to be generic, using some of the
existing Parent classes rather than RISC-V specific classes to
bring the same functionality to other Architectures.

The pass has been refactored, removing the RISC-V specific functions
and data-types and replacing them with datatypes that will support
all architectures and virtual functions in the respecitive classes
that allow support for the pass to be added. By default, this pass
will not run on on all architectures, only those that have the
`supportsInitUndef` function impletmented. This commit will only
refactor the exisiting code and add the pass in as a CodeGen pass rather
than target specific. To add support for other architectures, this should
be done in new, following commits.

This will allow for the pass to be used by any architecture. With the
correct overriding functions, other architectures can be supported
to provide the same functionality as was added to fix issue that
was reported in Issue #50157.

This is still a temporary measure, and a better more permenant fix
should be found, but for the time being this will allow for the
correct early-clobber contraint to be followed when defined in
vector instructions.


  Commit: 87a95f5411816d0cc07f390cab5ac961085b9d51
      https://github.com/llvm/llvm-project/commit/87a95f5411816d0cc07f390cab5ac961085b9d51
  Author: Jack Styles <jack.styles at arm.com>
  Date:   2024-02-15 (Thu, 15 Feb 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll

  Log Message:
  -----------
  [ARM] Add support for ARM Instructions for Init Undef Pass

For assembly instructions within the ARM Architecture, certain
instructions have early-clobber restraints that are defined
for the instruction. However, when using the Greedy register
allocator this is ignored. To get around this, we can use
the Init Undef pass to assign a Pseudo instruction for the
registers that are early-clobber to ensure the restraint
is followed.

This adds in support for this using a new Pseudo instruction,
`PseudoARMInitUndef` which is used to ensure early-clobber
restrains are followed. The relevant overriding functions
have also been provided to ensure the architecture is
supported by the pass and the required information can be
passed to ensure that early-clobber restrains are respected.


Compare: https://github.com/llvm/llvm-project/compare/5549e7b6df54...87a95f541181

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