[all-commits] [llvm/llvm-project] b8ed69: [RISCV] Support llvm.readsteadycounter intrinsic

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b8ed69ecc01385c03844e8fa05ba418a5670d322
      https://github.com/llvm/llvm-project/commit/b8ed69ecc01385c03844e8fa05ba418a5670d322
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/test/CodeGen/RISCV/readsteadycounter.ll

  Log Message:
  -----------
  [RISCV] Support llvm.readsteadycounter intrinsic

This intrinsic was introduced by #81331, which is a lot like
`llvm.readcyclecounter`.

For the RISCV implementation, we rename `ReadCycleWide` pseudo to
`ReadCounterWide` and make it accept two operands (the low and high
parts of the counter). As for legalization and lowering parts, we
reuse the code of `ISD::READCYCLECOUNTER` (make it able to handle
both intrinsics), and we use `time` CSR for `ISD::READSTEADYCOUNTER`.

Tests using Clang builtins are runned on real hardware and it works
as excepted.

Reviewers: asb, MaskRay, dtcxzyw, preames, topperc, jhuber6

Reviewed By: jhuber6, asb, MaskRay, dtcxzyw

Pull Request: https://github.com/llvm/llvm-project/pull/82322



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