[all-commits] [llvm/llvm-project] 798897: Implement convergence control in MIR using Selecti...

[Sameer Sahasrabuddhe via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79889734b940356ab3381423c93ae06f22e772c9
      https://github.com/llvm/llvm-project/commit/79889734b940356ab3381423c93ae06f22e772c9
  Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
  Date:   2024-02-21 (Wed, 21 Feb 2024)

  Changed paths:
    M llvm/include/llvm/ADT/GenericConvergenceVerifier.h
    M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    A llvm/include/llvm/CodeGen/MachineConvergenceVerifier.h
    M llvm/include/llvm/CodeGen/SelectionDAGISel.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/GenericConvergenceVerifierImpl.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/Target.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/CMakeLists.txt
    A llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/CodeGen/ValueTypes.cpp
    M llvm/lib/IR/ConvergenceVerifier.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/PowerPC/fmf-propagation.ll
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/lit.local.cfg
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/not-ssa.mir
    A llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
    M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
    M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td

  Log Message:
  -----------
  Implement convergence control in MIR using SelectionDAG (#71785)

LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.



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