[all-commits] [llvm/llvm-project] 3b4b04: [PowerPC] Mask constant operands in ValueBit track...

[Qiu Chaofan via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b4b0476423e2340cf6ef370df3c98420014c97b
      https://github.com/llvm/llvm-project/commit/3b4b0476423e2340cf6ef370df3c98420014c97b
  Author: Qiu Chaofan <qiucofan at cn.ibm.com>
  Date:   2024-02-20 (Tue, 20 Feb 2024)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    A llvm/test/CodeGen/PowerPC/pr59074.ll

  Log Message:
  -----------
  [PowerPC] Mask constant operands in ValueBit tracking (#67653)

In IR or C code, shift amount larger than value size is undefined
behavior. But in practice, backend lowering for shift_parts produces
add/sub of shift amounts, thus constant shift amounts might be
negative or larger than value size, which depends on ISA definition.

PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction)
will be taken, and if the highest among them is 1, result will be
zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift
amount.

This commit emulates the behavior and avoids array overflow in bit
permutation's value bits calculator.

(cherry picked from commit 292d9e869fcfc2ece694848db4022b0b939847e3)



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