[all-commits] [llvm/llvm-project] 61ae7e: [RISCV] Select pattern (shl (sext_vl/zext_vl), 1) ...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 61ae7e498253d72422cef853798fc2bee1c731cf
      https://github.com/llvm/llvm-project/commit/61ae7e498253d72422cef853798fc2bee1c731cf
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2024-02-20 (Tue, 20 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

  Log Message:
  -----------
  [RISCV] Select pattern (shl (sext_vl/zext_vl), 1) to VWADD/VWADDU. (#82225)

Previously, we already had similar selection pattern for (shl (ext)) and
(shl_vl (ext_vl)).



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications