[all-commits] [llvm/llvm-project] f668a0: [DAGCombiner][RISCV] Optimize (zext nneg (truncate...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f668a08e005962f9f68d7586f99fc431dbed9a88
      https://github.com/llvm/llvm-project/commit/f668a08e005962f9f68d7586f99fc431dbed9a88
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-19 (Mon, 19 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/CodeGen/VE/Scalar/ctlz.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (#82227)

This treats the zext nneg as sext if X is known to have sufficient sign
bits to allow the zext or truncate or both to removed. This code is
taken from the same optimization for sext.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications