[all-commits] [llvm/llvm-project] dd1897: [AArch64] Initial Ampere1B scheduling model (#81341)

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dd1897c6cb028bda7d4d541d1bb33965eccf0a68
      https://github.com/llvm/llvm-project/commit/dd1897c6cb028bda7d4d541d1bb33965eccf0a68
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2024-02-14 (Wed, 14 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    A llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkor.td
    M llvm/lib/Target/AArch64/AArch64SchedKryo.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s

  Log Message:
  -----------
  [AArch64] Initial Ampere1B scheduling model (#81341)

The Ampere1B core is enabled with a new scheduling/pipeline model, as it
provides significant updates over the Ampere1 core; it reduces latencies
on many instructions, has some micro-ops reassigned between the XY and X
units, and provides modelling for the instructions added since Ampere1
and Ampere1A.

As this is the first model implementing the CSSC instructions, we update
the UnsupportedFeatures on all other models (that have CompleteModel
set).
    
Testcases are added under llvm-mca: these showed the FullFP16 feature
missing, so we are adding it in as part of this commit.

This *adds tests and additional fixes* compared to the reverted #81338.