[all-commits] [llvm/llvm-project] 9838c8: [RISCV] Copy typepromotion-overflow.ll from AArch6...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9838c8512bc29e3a1b8edeb0eb2541160e4c727f
      https://github.com/llvm/llvm-project/commit/9838c8512bc29e3a1b8edeb0eb2541160e4c727f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-13 (Tue, 13 Feb 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/typepromotion-overflow.ll

  Log Message:
  -----------
  [RISCV] Copy typepromotion-overflow.ll from AArch64. NFC


  Commit: 7d40ea85d5ea5cc837536f61e3b4f80ea69f14d0
      https://github.com/llvm/llvm-project/commit/7d40ea85d5ea5cc837536f61e3b4f80ea69f14d0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-13 (Tue, 13 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/TypePromotion.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/signbit-test.ll
    M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
    M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll

  Log Message:
  -----------
  [RISCV] Enable the TypePromotion pass from AArch64/ARM.

This pass looks for unsigned icmps that have illegal types and tries
to widen the use/def graph to improve the placement of the zero
extends that type legalization would need to insert.

I've explicitly disabled it for i32 by adding a check for
isSExtCheaperThanZExt to the pass.

The generated code isn't perfect, but my data shows a net
dynamic instruction count improvement on spec2017 for both base and
Zba+Zbb+Zbs.


Compare: https://github.com/llvm/llvm-project/compare/742a06f577b4...7d40ea85d5ea