[all-commits] [llvm/llvm-project] 9be7b0: [IRGen][AArch64][RISCV] Generalize bitcast between...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9be7b0a539f673081bf8d1d5a5b08135190fd46d
      https://github.com/llvm/llvm-project/commit/9be7b0a539f673081bf8d1d5a5b08135190fd46d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-13 (Tue, 13 Feb 2024)

  Changed paths:
    M clang/lib/CodeGen/CGCall.cpp
    M clang/lib/CodeGen/CGExprScalar.cpp
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c

  Log Message:
  -----------
  [IRGen][AArch64][RISCV] Generalize bitcast between i1 predicate vector and i8 fixed vector. (#76548)

Instead of only handling vscale x 16 x i1 predicate vectors, handle any
scalable i1 vector where the known minimum is divisible by 8.

This is used on RISC-V where we have multiple sizes of predicate
types.