[all-commits] [llvm/llvm-project] bef25a: [X86] X86FixupVectorConstants - use explicit regis...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bef25ae297d6d246bf0fa8667c8b08f9d5e8dae7
      https://github.com/llvm/llvm-project/commit/bef25ae297d6d246bf0fa8667c8b08f9d5e8dae7
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-02-08 (Thu, 08 Feb 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
    M llvm/test/CodeGen/X86/pr81136.ll

  Log Message:
  -----------
  [X86] X86FixupVectorConstants - use explicit register bitwidth for the loaded vector instead of using constant pool bitwidth

Fixes #81136 - we might be loading from a constant pool entry wider than the destination register bitwidth, affecting the vextload scale calculation.

ConvertToBroadcastAVX512 doesn't yet set an explicit bitwidth (it will default to the constant pool bitwidth) due to difficulties in looking up the original register width through the fold tables, but as we only use rebuildSplatCst this shouldn't cause any miscompilations, although it might prevent folding to broadcast if only the lower bits match a splatable pattern.