[all-commits] [llvm/llvm-project] 5d4178: [AArch64] Alter latency of FCSEL under Cortex-A510...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
      https://github.com/llvm/llvm-project/commit/5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
  Author: David Green <david.green at arm.com>
  Date:   2024-02-01 (Thu, 01 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/test/CodeGen/AArch64/select_fmf.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s

  Log Message:
  -----------
  [AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)

As per the Cortex-A510 software optimization guide, the latency of a
fcsel should be 3 not 4. It would previously get the latency from
WriteF.