[all-commits] [llvm/llvm-project] 1d1432: [AArch64][SVE2] Generate urshr rounding shift righ...

[Usman Nadeem via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d1432356e656fcae7b2a3634a2b349334ba3d80
      https://github.com/llvm/llvm-project/commit/1d1432356e656fcae7b2a3634a2b349334ba3d80
  Author: Usman Nadeem <mnadeem at quicinc.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve2-rsh.ll

  Log Message:
  -----------
  [AArch64][SVE2] Generate urshr rounding shift rights (#78374)

Add a new node `AArch64ISD::URSHR_I_PRED`.

`srl(add(X, 1 << (ShiftValue - 1)), ShiftValue)` is transformed to
`urshr`, or to `rshrnb` (as before) if the result it truncated.

`uzp1(rshrnb(uunpklo(X),C), rshrnb(uunpkhi(X), C))` is converted to
`urshr(X, C)` (tested by the wide_trunc tests).

Pattern matching code in `canLowerSRLToRoundingShiftForVT` is taken
from prior code in rshrnb. It returns true if the add has NUW or if the
number of bits used in the return value allow us to not care about the
overflow (tested by rshrnb test cases).